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Searched refs:DP_RECEIVER_CAP_SIZE (Results 1 – 14 of 14) sorted by relevance

/Linux-v5.4/include/drm/
Ddrm_dp_helper.h1054 #define DP_RECEIVER_CAP_SIZE 0xf macro
1059 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1060 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1128 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate() argument
1134 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count() argument
1140 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_enhanced_frame_cap() argument
1147 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_tps3_supported() argument
1154 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_tps4_supported() argument
1161 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_training_pattern_mask() argument
1168 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_is_branch() argument
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Ddrm_dp_mst_helper.h514 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/Linux-v5.4/drivers/gpu/drm/rockchip/
Dcdn-dp-core.h101 u8 dpcd[DP_RECEIVER_CAP_SIZE];
Dcdn-dp-core.c369 DP_RECEIVER_CAP_SIZE); in cdn_dp_get_sink_capability()
/Linux-v5.4/drivers/gpu/drm/
Ddrm_dp_helper.c123 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { in drm_dp_link_train_clock_recovery_delay() argument
138 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { in drm_dp_link_train_channel_eq_delay() argument
477 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_clock() argument
508 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_bpc() argument
565 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_debug() argument
Ddrm_dp_mst_topology.c2707 ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_mst_topology_mgr_set_mst()
2708 if (ret != DP_RECEIVER_CAP_SIZE) { in drm_dp_mst_topology_mgr_set_mst()
2808 sret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_mst_topology_mgr_resume()
2809 if (sret != DP_RECEIVER_CAP_SIZE) { in drm_dp_mst_topology_mgr_resume()
3699 ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, buf, DP_RECEIVER_CAP_SIZE); in drm_dp_mst_dump_topology()
3700 seq_printf(m, "dpcd: %*ph\n", DP_RECEIVER_CAP_SIZE, buf); in drm_dp_mst_dump_topology()
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Datombios_dp.c41 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
485 u8 dpcd[DP_RECEIVER_CAP_SIZE];
745 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); in amdgpu_atombios_dp_link_train()
Damdgpu_mode.h471 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/Linux-v5.4/drivers/gpu/drm/radeon/
Datombios_dp.c37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
547 u8 dpcd[DP_RECEIVER_CAP_SIZE];
844 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); in radeon_dp_link_train()
Dradeon_mode.h490 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/Linux-v5.4/drivers/gpu/drm/msm/edp/
Dedp_ctrl.c96 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1189 DP_RECEIVER_CAP_SIZE) < DP_RECEIVER_CAP_SIZE) { in msm_edp_ctrl_panel_connected()
1191 memset(ctrl->dpcd, 0, DP_RECEIVER_CAP_SIZE); in msm_edp_ctrl_panel_connected()
/Linux-v5.4/drivers/gpu/drm/bridge/
Danalogix-anx78xx.c77 u8 dpcd[DP_RECEIVER_CAP_SIZE];
781 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); in anx78xx_dp_link_training()
/Linux-v5.4/drivers/gpu/drm/i915/display/
Dintel_display_types.h1157 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_debugfs.c4399 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },