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Searched refs:DPU_REG_WRITE (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_util.c145 DPU_REG_WRITE(c, in _dpu_hw_setup_scaler3_lut()
155 DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0)); in _dpu_hw_setup_scaler3_lut()
193 DPU_REG_WRITE(c, QSEED3_DE_SHARPEN + offset, sharp_lvl); in _dpu_hw_setup_scaler3_de()
194 DPU_REG_WRITE(c, QSEED3_DE_SHARPEN_CTL + offset, sharp_ctl); in _dpu_hw_setup_scaler3_de()
195 DPU_REG_WRITE(c, QSEED3_DE_SHAPE_CTL + offset, shape_ctl); in _dpu_hw_setup_scaler3_de()
196 DPU_REG_WRITE(c, QSEED3_DE_THRESHOLD + offset, de_thr); in _dpu_hw_setup_scaler3_de()
197 DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_0 + offset, adjust_a); in _dpu_hw_setup_scaler3_de()
198 DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_1 + offset, adjust_b); in _dpu_hw_setup_scaler3_de()
199 DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_2 + offset, adjust_c); in _dpu_hw_setup_scaler3_de()
255 DPU_REG_WRITE(c, QSEED3_PHASE_INIT + scaler_offset, phase_init); in dpu_hw_setup_scaler3()
[all …]
Ddpu_hw_intf.c169 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); in dpu_hw_intf_setup_timing_engine()
170 DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); in dpu_hw_intf_setup_timing_engine()
171 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0, in dpu_hw_intf_setup_timing_engine()
173 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl); in dpu_hw_intf_setup_timing_engine()
174 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start); in dpu_hw_intf_setup_timing_engine()
175 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end); in dpu_hw_intf_setup_timing_engine()
176 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl); in dpu_hw_intf_setup_timing_engine()
177 DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start); in dpu_hw_intf_setup_timing_engine()
178 DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end); in dpu_hw_intf_setup_timing_engine()
179 DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr); in dpu_hw_intf_setup_timing_engine()
[all …]
Ddpu_hw_sspp.c191 DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask); in dpu_hw_sspp_setup_multirect()
212 DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode); in _sspp_setup_opmode()
230 DPU_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode); in _sspp_setup_csc10_opmode()
302 DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, in dpu_hw_sspp_setup_format()
307 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, in dpu_hw_sspp_setup_format()
331 DPU_REG_WRITE(c, format_off + idx, src_format); in dpu_hw_sspp_setup_format()
332 DPU_REG_WRITE(c, unpack_pat_off + idx, unpack); in dpu_hw_sspp_setup_format()
333 DPU_REG_WRITE(c, op_mode_off + idx, opmode); in dpu_hw_sspp_setup_format()
336 DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31)); in dpu_hw_sspp_setup_format()
379 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR + idx, lr_pe[0]); in dpu_hw_sspp_setup_pe_config()
[all …]
Ddpu_hw_lm.c73 DPU_REG_WRITE(c, LM_OUT_SIZE, outsize); in dpu_hw_lm_setup_out()
80 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); in dpu_hw_lm_setup_out()
90 DPU_REG_WRITE(c, LM_BORDER_COLOR_0, in dpu_hw_lm_setup_border_color()
93 DPU_REG_WRITE(c, LM_BORDER_COLOR_1, in dpu_hw_lm_setup_border_color()
114 DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha); in dpu_hw_lm_setup_blend_config_sdm845()
115 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); in dpu_hw_lm_setup_blend_config_sdm845()
131 DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); in dpu_hw_lm_setup_blend_config()
132 DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); in dpu_hw_lm_setup_blend_config()
133 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); in dpu_hw_lm_setup_blend_config()
147 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); in dpu_hw_lm_setup_color3()
Ddpu_hw_pingpong.c68 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); in dpu_hw_pp_setup_te_config()
69 DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height); in dpu_hw_pp_setup_te_config()
70 DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val); in dpu_hw_pp_setup_te_config()
71 DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq); in dpu_hw_pp_setup_te_config()
72 DPU_REG_WRITE(c, PP_START_POS, te->start_pos); in dpu_hw_pp_setup_te_config()
73 DPU_REG_WRITE(c, PP_SYNC_THRESH, in dpu_hw_pp_setup_te_config()
76 DPU_REG_WRITE(c, PP_SYNC_WRCOUNT, in dpu_hw_pp_setup_te_config()
107 DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, enable); in dpu_hw_pp_enable_te()
128 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); in dpu_hw_pp_connect_external_te()
Ddpu_hw_ctl.c78 DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1); in dpu_hw_ctl_trigger_start()
85 DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1); in dpu_hw_ctl_trigger_pending()
112 DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); in dpu_hw_ctl_trigger_flush()
252 DPU_REG_WRITE(c, CTL_SW_RESET, 0x1); in dpu_hw_ctl_reset_control()
284 DPU_REG_WRITE(c, CTL_LAYER(LM_0 + i), 0); in dpu_hw_ctl_clear_all_blendstages()
285 DPU_REG_WRITE(c, CTL_LAYER_EXT(LM_0 + i), 0); in dpu_hw_ctl_clear_all_blendstages()
286 DPU_REG_WRITE(c, CTL_LAYER_EXT2(LM_0 + i), 0); in dpu_hw_ctl_clear_all_blendstages()
287 DPU_REG_WRITE(c, CTL_LAYER_EXT3(LM_0 + i), 0); in dpu_hw_ctl_clear_all_blendstages()
419 DPU_REG_WRITE(c, CTL_LAYER(lm), mixercfg); in dpu_hw_ctl_setup_blendstage()
420 DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext); in dpu_hw_ctl_setup_blendstage()
[all …]
Ddpu_hw_top.c86 DPU_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0); in dpu_hw_setup_split_pipe()
87 DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe); in dpu_hw_setup_split_pipe()
88 DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe); in dpu_hw_setup_split_pipe()
89 DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1); in dpu_hw_setup_split_pipe()
118 DPU_REG_WRITE(c, reg_off, new_val); in dpu_hw_setup_clk_force_ctrl()
176 DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg); in dpu_hw_setup_vsync_source()
209 DPU_REG_WRITE(c, wd_load_value, in dpu_hw_setup_vsync_source()
212 DPU_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */ in dpu_hw_setup_vsync_source()
216 DPU_REG_WRITE(c, wd_ctl2, reg); in dpu_hw_setup_vsync_source()
265 DPU_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static); in dpu_hw_reset_ubwc()
[all …]
Ddpu_hw_vbif.c52 DPU_REG_WRITE(c, VBIF_XIN_CLR_ERR, pnd | src); in dpu_hw_clear_errors()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
103 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_limit_conf()
141 DPU_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val); in dpu_hw_set_halt_ctrl()
180 DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val); in dpu_hw_set_qos_remap()
181 DPU_REG_WRITE(c, VBIF_XINL_QOS_LVL_REMAP_000 + reg_high, reg_val_lvl); in dpu_hw_set_qos_remap()
196 DPU_REG_WRITE(c, VBIF_WRITE_GATHER_EN, reg_val); in dpu_hw_set_write_gather_en()
Ddpu_hw_interrupts.c871 DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); in dpu_hw_intr_enable_irq()
873 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); in dpu_hw_intr_enable_irq()
916 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); in dpu_hw_intr_disable_irq_nolock()
918 DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); in dpu_hw_intr_disable_irq_nolock()
959 DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off, 0xffffffff); in dpu_hw_intr_clear_irqs()
975 DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].en_off, 0x00000000); in dpu_hw_intr_disable_irqs()
1003 DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off, in dpu_hw_intr_get_interrupt_statuses()
1025 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, in dpu_hw_intr_clear_intr_status_nolock()
1054 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, in dpu_hw_intr_get_interrupt_status()
Ddpu_hw_util.h306 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off) macro