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Searched refs:DPU_REG_READ (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_vbif.c44 pnd = DPU_REG_READ(c, VBIF_XIN_PND_ERR); in dpu_hw_clear_errors()
45 src = DPU_REG_READ(c, VBIF_XIN_SRC_ERR); in dpu_hw_clear_errors()
79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
100 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf()
122 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_get_limit_conf()
134 reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL0); in dpu_hw_set_halt_ctrl()
150 reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL1); in dpu_hw_get_halt_ctrl()
169 reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high); in dpu_hw_set_qos_remap()
170 reg_val_lvl = DPU_REG_READ(c, VBIF_XINL_QOS_LVL_REMAP_000 + reg_high); in dpu_hw_set_qos_remap()
194 reg_val = DPU_REG_READ(c, VBIF_WRITE_GATHER_EN); in dpu_hw_set_write_gather_en()
Ddpu_hw_pingpong.c122 cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC); in dpu_hw_pp_connect_external_te()
144 val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL); in dpu_hw_pp_get_vsync_info()
147 val = DPU_REG_READ(c, PP_INT_COUNT_VAL); in dpu_hw_pp_get_vsync_info()
151 val = DPU_REG_READ(c, PP_LINE_COUNT); in dpu_hw_pp_get_vsync_info()
167 init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF; in dpu_hw_pp_get_line_count()
168 height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF; in dpu_hw_pp_get_line_count()
173 line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF; in dpu_hw_pp_get_line_count()
Ddpu_hw_intf.c97 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); in dpu_hw_intf_setup_timing_engine()
209 fetch_enable = DPU_REG_READ(c, INTF_CONFIG); in dpu_hw_intf_setup_prg_fetch()
227 s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); in dpu_hw_intf_get_status()
229 s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT); in dpu_hw_intf_get_status()
230 s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT); in dpu_hw_intf_get_status()
246 return DPU_REG_READ(c, INTF_LINE_COUNT); in dpu_hw_intf_get_line_count()
Ddpu_hw_top.c111 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_setup_clk_force_ctrl()
137 value = DPU_REG_READ(c, DANGER_STATUS); in dpu_hw_get_danger_status()
166 reg = DPU_REG_READ(c, MDP_VSYNC_SEL); in dpu_hw_setup_vsync_source()
213 reg = DPU_REG_READ(c, wd_ctl2); in dpu_hw_setup_vsync_source()
234 value = DPU_REG_READ(c, SAFE_STATUS); in dpu_hw_get_safe_status()
Ddpu_hw_sspp.c183 mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx); in dpu_hw_sspp_setup_multirect()
205 opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx); in _sspp_setup_opmode()
224 opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx); in _sspp_setup_csc10_opmode()
261 opmode = DPU_REG_READ(c, op_mode_off + idx); in dpu_hw_sspp_setup_format()
469 ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx); in dpu_hw_sspp_setup_rects()
470 ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx); in dpu_hw_sspp_setup_rects()
Ddpu_hw_lm.c70 op_mode = DPU_REG_READ(c, LM_OP_MODE); in dpu_hw_lm_setup_out()
143 op_mode = DPU_REG_READ(c, LM_OP_MODE); in dpu_hw_lm_setup_color3()
Ddpu_hw_ctl.c71 return DPU_REG_READ(c, CTL_FLUSH); in dpu_hw_ctl_get_flush_register()
238 status = DPU_REG_READ(c, CTL_SW_RESET); in dpu_hw_ctl_poll_reset_status()
264 status = DPU_REG_READ(c, CTL_SW_RESET); in dpu_hw_ctl_wait_reset_status()
Ddpu_hw_util.h307 #define DPU_REG_READ(c, off) dpu_reg_read(c, off) macro
Ddpu_hw_interrupts.c995 intr->save_irq_status[i] = DPU_REG_READ(&intr->hw, in dpu_hw_intr_get_interrupt_statuses()
999 enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off); in dpu_hw_intr_get_interrupt_statuses()
1050 intr_status = DPU_REG_READ(&intr->hw, in dpu_hw_intr_get_interrupt_status()
Ddpu_hw_util.c305 return DPU_REG_READ(c, QSEED3_HW_VERSION + scaler_offset); in dpu_hw_get_scaler3_ver()