Searched refs:DPR (Results 1 – 8 of 8) sorted by relevance
260 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
299 #define DPR 0x01 /* Disable Pipe Req */ macro
1807 np->rv_ccntl0 |= DPR;
595 #define DPR 0x01 macro1954 if (status1 & DPR) { in ahc_pci_intr()1963 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { in ahc_pci_intr()
736 #define DPR 0x01 macro
1150 field DPR 0x011168 field DPR 0x011184 field DPR 0x011201 field DPR 0x011217 field DPR 0x011232 field DPR 0x01
1303 #define DPR 0x01
823 #define DPR 0x01 /* Disable Pipe Req */ macro
