Searched refs:DPLL_FPA01_P1_POST_DIV_SHIFT (Results 1 – 5 of 5) sorted by relevance
338 DPLL_FPA01_P1_POST_DIV_SHIFT); in psb_intel_crtc_clock_get()354 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in psb_intel_crtc_clock_get()
879 DPLL_FPA01_P1_POST_DIV_SHIFT); in cdv_intel_crtc_clock_get()899 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in cdv_intel_crtc_clock_get()
254 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 macro
8031 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()8084 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()8089 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()9601 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()11316 DPLL_FPA01_P1_POST_DIV_SHIFT); in i9xx_crtc_clock_get()11343 DPLL_FPA01_P1_POST_DIV_SHIFT); in i9xx_crtc_clock_get()11354 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in i9xx_crtc_clock_get()16307 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | in i830_enable_pipe()
3320 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 macro
