Searched refs:DPLL_CTRL1_LINK_RATE_MASK (Results 1 – 4 of 4) sorted by relevance
845 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { in skl_dpll0_update()857 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); in skl_dpll0_update()958 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); in skl_dpll0_enable()
994 DPLL_CTRL1_LINK_RATE_MASK(id)); in skl_ddi_pll_write_ctrl1()
1573 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0); in skl_ddi_clock_get()
9671 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) macro
