Searched refs:DMA_CHAN_TX_CONTROL (Results 1 – 3 of 3) sorted by relevance
92 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_init_tx_chan()98 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_init_tx_chan()143 reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] = in _dwmac4_dump_dma_regs()144 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); in _dwmac4_dump_dma_regs()400 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tso()402 ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tso()405 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tso()407 ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tso()
47 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_start_tx()50 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_start_tx()59 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_stop_tx()62 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_stop_tx()
92 #define DMA_CHAN_TX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x4) macro
