Searched refs:DMA_CHAN_RX_CONTROL (Results 1 – 3 of 3) sorted by relevance
71 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_start_rx()75 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_start_rx()84 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_stop_rx()87 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_stop_rx()
78 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_init_rx_chan()80 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_init_rx_chan()145 reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] = in _dwmac4_dump_dma_regs()146 readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); in _dwmac4_dump_dma_regs()426 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_set_bfsize()431 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_set_bfsize()
93 #define DMA_CHAN_RX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x8) macro
