Searched refs:DISPLAY_PLANE_ENABLE (Results 1 – 13 of 13) sorted by relevance
244 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in mdfld_disable_crtc()246 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_disable_crtc()356 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in mdfld_crtc_dpms()358 temp | DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()384 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()400 temp | DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()432 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in mdfld_crtc_dpms()434 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()850 dev_priv->dspcntr[pipe] |= DISPLAY_PLANE_ENABLE; in mdfld_crtc_mode_set()
360 dspcntr |= DISPLAY_PLANE_ENABLE; in oaktrail_crtc_hdmi_mode_set()394 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in oaktrail_crtc_hdmi_dpms()395 REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE); in oaktrail_crtc_hdmi_dpms()462 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in oaktrail_crtc_hdmi_dpms()463 REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE); in oaktrail_crtc_hdmi_dpms()
267 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in oaktrail_crtc_dpms()269 temp | DISPLAY_PLANE_ENABLE, in oaktrail_crtc_dpms()293 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in oaktrail_crtc_dpms()295 temp & ~DISPLAY_PLANE_ENABLE, i); in oaktrail_crtc_dpms()
233 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in gma_crtc_dpms()235 temp | DISPLAY_PLANE_ENABLE); in gma_crtc_dpms()280 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in gma_crtc_dpms()282 temp & ~DISPLAY_PLANE_ENABLE); in gma_crtc_dpms()
347 PSB_WVDC32(pipe->cntr & ~DISPLAY_PLANE_ENABLE, map->cntr); in mdfld_restore_display_registers()
201 dspcntr |= DISPLAY_PLANE_ENABLE; in psb_intel_crtc_mode_set()
624 #define DISPLAY_PLANE_ENABLE (1 << 31) macro
723 dspcntr |= DISPLAY_PLANE_ENABLE; in cdv_intel_crtc_mode_set()
214 plane->enabled = !!(val & DISPLAY_PLANE_ENABLE); in intel_vgpu_decode_primary_plane()
299 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; in emulate_monitor_status_change()
1592 if (!(val & DISPLAY_PLANE_ENABLE)) in vlv_dsi_get_hw_panel_orientation()
3622 dspcntr = DISPLAY_PLANE_ENABLE; in i9xx_plane_ctl()3899 ret = val & DISPLAY_PLANE_ENABLE; in i9xx_plane_get_hw_state()16362 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()16363 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()16364 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()
6213 #define DISPLAY_PLANE_ENABLE (1 << 31) macro
