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Searched refs:DIDT_SQ_CTRL0__PHASE_OFFSET_MASK (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/powerplay/hwmgr/
Dsmu7_powertune.c144 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
286 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
428 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
571 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
754 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
Dvega10_powertune.c212 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFF…
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h18271 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc macro
Dgfx_8_1_sh_mask.h21091 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc macro
Dgfx_8_0_sh_mask.h20489 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h28699 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK … macro
Dgc_9_2_1_sh_mask.h30265 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK … macro
Dgc_9_1_sh_mask.h29942 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK … macro
Dgc_10_1_0_sh_mask.h42921 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK … macro