1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 4 */ 5 6 #ifndef __MESON_REGISTERS_H 7 #define __MESON_REGISTERS_H 8 9 #include <linux/io.h> 10 11 /* Shift all registers by 2 */ 12 #define _REG(reg) ((reg) << 2) 13 14 #define writel_bits_relaxed(mask, val, addr) \ 15 writel_relaxed((readl_relaxed(addr) & ~(mask)) | ((val) & (mask)), addr) 16 17 /* vpp2 */ 18 #define VPP2_DUMMY_DATA 0x1900 19 #define VPP2_LINE_IN_LENGTH 0x1901 20 #define VPP2_PIC_IN_HEIGHT 0x1902 21 #define VPP2_SCALE_COEF_IDX 0x1903 22 #define VPP2_SCALE_COEF 0x1904 23 #define VPP2_VSC_REGION12_STARTP 0x1905 24 #define VPP2_VSC_REGION34_STARTP 0x1906 25 #define VPP2_VSC_REGION4_ENDP 0x1907 26 #define VPP2_VSC_START_PHASE_STEP 0x1908 27 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909 28 #define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a 29 #define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b 30 #define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c 31 #define VPP2_VSC_PHASE_CTRL 0x190d 32 #define VPP2_VSC_INI_PHASE 0x190e 33 #define VPP2_HSC_REGION12_STARTP 0x1910 34 #define VPP2_HSC_REGION34_STARTP 0x1911 35 #define VPP2_HSC_REGION4_ENDP 0x1912 36 #define VPP2_HSC_START_PHASE_STEP 0x1913 37 #define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914 38 #define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915 39 #define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916 40 #define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917 41 #define VPP2_HSC_PHASE_CTRL 0x1918 42 #define VPP2_SC_MISC 0x1919 43 #define VPP2_PREBLEND_VD1_H_START_END 0x191a 44 #define VPP2_PREBLEND_VD1_V_START_END 0x191b 45 #define VPP2_POSTBLEND_VD1_H_START_END 0x191c 46 #define VPP2_POSTBLEND_VD1_V_START_END 0x191d 47 #define VPP2_PREBLEND_H_SIZE 0x1920 48 #define VPP2_POSTBLEND_H_SIZE 0x1921 49 #define VPP2_HOLD_LINES 0x1922 50 #define VPP2_BLEND_ONECOLOR_CTRL 0x1923 51 #define VPP2_PREBLEND_CURRENT_XY 0x1924 52 #define VPP2_POSTBLEND_CURRENT_XY 0x1925 53 #define VPP2_MISC 0x1926 54 #define VPP2_OFIFO_SIZE 0x1927 55 #define VPP2_FIFO_STATUS 0x1928 56 #define VPP2_SMOKE_CTRL 0x1929 57 #define VPP2_SMOKE1_VAL 0x192a 58 #define VPP2_SMOKE2_VAL 0x192b 59 #define VPP2_SMOKE1_H_START_END 0x192d 60 #define VPP2_SMOKE1_V_START_END 0x192e 61 #define VPP2_SMOKE2_H_START_END 0x192f 62 #define VPP2_SMOKE2_V_START_END 0x1930 63 #define VPP2_SCO_FIFO_CTRL 0x1933 64 #define VPP2_HSC_PHASE_CTRL1 0x1934 65 #define VPP2_HSC_INI_PAT_CTRL 0x1935 66 #define VPP2_VADJ_CTRL 0x1940 67 #define VPP2_VADJ1_Y 0x1941 68 #define VPP2_VADJ1_MA_MB 0x1942 69 #define VPP2_VADJ1_MC_MD 0x1943 70 #define VPP2_VADJ2_Y 0x1944 71 #define VPP2_VADJ2_MA_MB 0x1945 72 #define VPP2_VADJ2_MC_MD 0x1946 73 #define VPP2_MATRIX_PROBE_COLOR 0x195c 74 #define VPP2_MATRIX_HL_COLOR 0x195d 75 #define VPP2_MATRIX_PROBE_POS 0x195e 76 #define VPP2_MATRIX_CTRL 0x195f 77 #define VPP2_MATRIX_COEF00_01 0x1960 78 #define VPP2_MATRIX_COEF02_10 0x1961 79 #define VPP2_MATRIX_COEF11_12 0x1962 80 #define VPP2_MATRIX_COEF20_21 0x1963 81 #define VPP2_MATRIX_COEF22 0x1964 82 #define VPP2_MATRIX_OFFSET0_1 0x1965 83 #define VPP2_MATRIX_OFFSET2 0x1966 84 #define VPP2_MATRIX_PRE_OFFSET0_1 0x1967 85 #define VPP2_MATRIX_PRE_OFFSET2 0x1968 86 #define VPP2_DUMMY_DATA1 0x1969 87 #define VPP2_GAINOFF_CTRL0 0x196a 88 #define VPP2_GAINOFF_CTRL1 0x196b 89 #define VPP2_GAINOFF_CTRL2 0x196c 90 #define VPP2_GAINOFF_CTRL3 0x196d 91 #define VPP2_GAINOFF_CTRL4 0x196e 92 #define VPP2_CHROMA_ADDR_PORT 0x1970 93 #define VPP2_CHROMA_DATA_PORT 0x1971 94 #define VPP2_GCLK_CTRL0 0x1972 95 #define VPP2_GCLK_CTRL1 0x1973 96 #define VPP2_SC_GCLK_CTRL 0x1974 97 #define VPP2_MISC1 0x1976 98 #define VPP2_DNLP_CTRL_00 0x1981 99 #define VPP2_DNLP_CTRL_01 0x1982 100 #define VPP2_DNLP_CTRL_02 0x1983 101 #define VPP2_DNLP_CTRL_03 0x1984 102 #define VPP2_DNLP_CTRL_04 0x1985 103 #define VPP2_DNLP_CTRL_05 0x1986 104 #define VPP2_DNLP_CTRL_06 0x1987 105 #define VPP2_DNLP_CTRL_07 0x1988 106 #define VPP2_DNLP_CTRL_08 0x1989 107 #define VPP2_DNLP_CTRL_09 0x198a 108 #define VPP2_DNLP_CTRL_10 0x198b 109 #define VPP2_DNLP_CTRL_11 0x198c 110 #define VPP2_DNLP_CTRL_12 0x198d 111 #define VPP2_DNLP_CTRL_13 0x198e 112 #define VPP2_DNLP_CTRL_14 0x198f 113 #define VPP2_DNLP_CTRL_15 0x1990 114 #define VPP2_VE_ENABLE_CTRL 0x19a1 115 #define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2 116 #define VPP2_VE_DEMO_CENTER_BAR 0x19a3 117 #define VPP2_VE_H_V_SIZE 0x19a4 118 #define VPP2_VDO_MEAS_CTRL 0x19a8 119 #define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9 120 #define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa 121 #define VPP2_OSD_VSC_PHASE_STEP 0x19c0 122 #define VPP2_OSD_VSC_INI_PHASE 0x19c1 123 #define VPP2_OSD_VSC_CTRL0 0x19c2 124 #define VPP2_OSD_HSC_PHASE_STEP 0x19c3 125 #define VPP2_OSD_HSC_INI_PHASE 0x19c4 126 #define VPP2_OSD_HSC_CTRL0 0x19c5 127 #define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6 128 #define VPP2_OSD_SC_DUMMY_DATA 0x19c7 129 #define VPP2_OSD_SC_CTRL0 0x19c8 130 #define VPP2_OSD_SCI_WH_M1 0x19c9 131 #define VPP2_OSD_SCO_H_START_END 0x19ca 132 #define VPP2_OSD_SCO_V_START_END 0x19cb 133 #define VPP2_OSD_SCALE_COEF_IDX 0x19cc 134 #define VPP2_OSD_SCALE_COEF 0x19cd 135 #define VPP2_INT_LINE_NUM 0x19ce 136 137 /* viu */ 138 #define VIU_ADDR_START 0x1a00 139 #define VIU_ADDR_END 0x1aff 140 #define VIU_SW_RESET 0x1a01 141 #define VIU_SW_RESET_OSD1 BIT(0) 142 #define VIU_MISC_CTRL0 0x1a06 143 #define VIU_CTRL0_VD1_AFBC_MASK 0x170000 144 #define VIU_MISC_CTRL1 0x1a07 145 #define D2D3_INTF_LENGTH 0x1a08 146 #define D2D3_INTF_CTRL0 0x1a09 147 #define VIU_OSD1_CTRL_STAT 0x1a10 148 #define VIU_OSD1_OSD_BLK_ENABLE BIT(0) 149 #define VIU_OSD1_POSTBLD_SRC_VD1 (1 << 8) 150 #define VIU_OSD1_POSTBLD_SRC_VD2 (2 << 8) 151 #define VIU_OSD1_POSTBLD_SRC_OSD1 (3 << 8) 152 #define VIU_OSD1_POSTBLD_SRC_OSD2 (4 << 8) 153 #define VIU_OSD1_OSD_ENABLE BIT(21) 154 #define VIU_OSD1_CTRL_STAT2 0x1a2d 155 #define VIU_OSD1_COLOR_ADDR 0x1a11 156 #define VIU_OSD1_COLOR 0x1a12 157 #define VIU_OSD1_TCOLOR_AG0 0x1a17 158 #define VIU_OSD1_TCOLOR_AG1 0x1a18 159 #define VIU_OSD1_TCOLOR_AG2 0x1a19 160 #define VIU_OSD1_TCOLOR_AG3 0x1a1a 161 #define VIU_OSD1_BLK0_CFG_W0 0x1a1b 162 #define VIU_OSD1_BLK1_CFG_W0 0x1a1f 163 #define VIU_OSD1_BLK2_CFG_W0 0x1a23 164 #define VIU_OSD1_BLK3_CFG_W0 0x1a27 165 #define VIU_OSD1_BLK0_CFG_W1 0x1a1c 166 #define VIU_OSD1_BLK1_CFG_W1 0x1a20 167 #define VIU_OSD1_BLK2_CFG_W1 0x1a24 168 #define VIU_OSD1_BLK3_CFG_W1 0x1a28 169 #define VIU_OSD1_BLK0_CFG_W2 0x1a1d 170 #define VIU_OSD1_BLK1_CFG_W2 0x1a21 171 #define VIU_OSD1_BLK2_CFG_W2 0x1a25 172 #define VIU_OSD1_BLK3_CFG_W2 0x1a29 173 #define VIU_OSD1_BLK0_CFG_W3 0x1a1e 174 #define VIU_OSD1_BLK1_CFG_W3 0x1a22 175 #define VIU_OSD1_BLK2_CFG_W3 0x1a26 176 #define VIU_OSD1_BLK3_CFG_W3 0x1a2a 177 #define VIU_OSD1_BLK0_CFG_W4 0x1a13 178 #define VIU_OSD1_BLK1_CFG_W4 0x1a14 179 #define VIU_OSD1_BLK2_CFG_W4 0x1a15 180 #define VIU_OSD1_BLK3_CFG_W4 0x1a16 181 #define VIU_OSD1_FIFO_CTRL_STAT 0x1a2b 182 #define VIU_OSD1_TEST_RDDATA 0x1a2c 183 #define VIU_OSD1_PROT_CTRL 0x1a2e 184 #define VIU_OSD2_CTRL_STAT 0x1a30 185 #define VIU_OSD2_CTRL_STAT2 0x1a4d 186 #define VIU_OSD2_COLOR_ADDR 0x1a31 187 #define VIU_OSD2_COLOR 0x1a32 188 #define VIU_OSD2_HL1_H_START_END 0x1a33 189 #define VIU_OSD2_HL1_V_START_END 0x1a34 190 #define VIU_OSD2_HL2_H_START_END 0x1a35 191 #define VIU_OSD2_HL2_V_START_END 0x1a36 192 #define VIU_OSD2_TCOLOR_AG0 0x1a37 193 #define VIU_OSD2_TCOLOR_AG1 0x1a38 194 #define VIU_OSD2_TCOLOR_AG2 0x1a39 195 #define VIU_OSD2_TCOLOR_AG3 0x1a3a 196 #define VIU_OSD2_BLK0_CFG_W0 0x1a3b 197 #define VIU_OSD2_BLK1_CFG_W0 0x1a3f 198 #define VIU_OSD2_BLK2_CFG_W0 0x1a43 199 #define VIU_OSD2_BLK3_CFG_W0 0x1a47 200 #define VIU_OSD2_BLK0_CFG_W1 0x1a3c 201 #define VIU_OSD2_BLK1_CFG_W1 0x1a40 202 #define VIU_OSD2_BLK2_CFG_W1 0x1a44 203 #define VIU_OSD2_BLK3_CFG_W1 0x1a48 204 #define VIU_OSD2_BLK0_CFG_W2 0x1a3d 205 #define VIU_OSD2_BLK1_CFG_W2 0x1a41 206 #define VIU_OSD2_BLK2_CFG_W2 0x1a45 207 #define VIU_OSD2_BLK3_CFG_W2 0x1a49 208 #define VIU_OSD2_BLK0_CFG_W3 0x1a3e 209 #define VIU_OSD2_BLK1_CFG_W3 0x1a42 210 #define VIU_OSD2_BLK2_CFG_W3 0x1a46 211 #define VIU_OSD2_BLK3_CFG_W3 0x1a4a 212 #define VIU_OSD2_BLK0_CFG_W4 0x1a64 213 #define VIU_OSD2_BLK1_CFG_W4 0x1a65 214 #define VIU_OSD2_BLK2_CFG_W4 0x1a66 215 #define VIU_OSD2_BLK3_CFG_W4 0x1a67 216 #define VIU_OSD2_FIFO_CTRL_STAT 0x1a4b 217 #define VIU_OSD2_TEST_RDDATA 0x1a4c 218 #define VIU_OSD2_PROT_CTRL 0x1a4e 219 #define VIU_OSD2_MALI_UNPACK_CTRL 0x1abd 220 #define VIU_OSD2_DIMM_CTRL 0x1acf 221 222 #define VIU_OSD3_CTRL_STAT 0x3d80 223 #define VIU_OSD3_CTRL_STAT2 0x3d81 224 #define VIU_OSD3_COLOR_ADDR 0x3d82 225 #define VIU_OSD3_COLOR 0x3d83 226 #define VIU_OSD3_TCOLOR_AG0 0x3d84 227 #define VIU_OSD3_TCOLOR_AG1 0x3d85 228 #define VIU_OSD3_TCOLOR_AG2 0x3d86 229 #define VIU_OSD3_TCOLOR_AG3 0x3d87 230 #define VIU_OSD3_BLK0_CFG_W0 0x3d88 231 #define VIU_OSD3_BLK0_CFG_W1 0x3d8c 232 #define VIU_OSD3_BLK0_CFG_W2 0x3d90 233 #define VIU_OSD3_BLK0_CFG_W3 0x3d94 234 #define VIU_OSD3_BLK0_CFG_W4 0x3d98 235 #define VIU_OSD3_BLK1_CFG_W4 0x3d99 236 #define VIU_OSD3_BLK2_CFG_W4 0x3d9a 237 #define VIU_OSD3_FIFO_CTRL_STAT 0x3d9c 238 #define VIU_OSD3_TEST_RDDATA 0x3d9d 239 #define VIU_OSD3_PROT_CTRL 0x3d9e 240 #define VIU_OSD3_MALI_UNPACK_CTRL 0x3d9f 241 #define VIU_OSD3_DIMM_CTRL 0x3da0 242 243 #define VIU_OSD_DDR_PRIORITY_URGENT BIT(0) 244 #define VIU_OSD_HOLD_FIFO_LINES(lines) ((lines & 0x1f) << 5) 245 #define VIU_OSD_FIFO_DEPTH_VAL(val) ((val & 0x7f) << 12) 246 #define VIU_OSD_WORDS_PER_BURST(words) (((words & 0x4) >> 1) << 22) 247 #define VIU_OSD_FIFO_LIMITS(size) ((size & 0xf) << 24) 248 249 #define VD1_IF0_GEN_REG 0x1a50 250 #define VD1_IF0_CANVAS0 0x1a51 251 #define VD1_IF0_CANVAS1 0x1a52 252 #define VD1_IF0_LUMA_X0 0x1a53 253 #define VD1_IF0_LUMA_Y0 0x1a54 254 #define VD1_IF0_CHROMA_X0 0x1a55 255 #define VD1_IF0_CHROMA_Y0 0x1a56 256 #define VD1_IF0_LUMA_X1 0x1a57 257 #define VD1_IF0_LUMA_Y1 0x1a58 258 #define VD1_IF0_CHROMA_X1 0x1a59 259 #define VD1_IF0_CHROMA_Y1 0x1a5a 260 #define VD1_IF0_RPT_LOOP 0x1a5b 261 #define VD1_IF0_LUMA0_RPT_PAT 0x1a5c 262 #define VD1_IF0_CHROMA0_RPT_PAT 0x1a5d 263 #define VD1_IF0_LUMA1_RPT_PAT 0x1a5e 264 #define VD1_IF0_CHROMA1_RPT_PAT 0x1a5f 265 #define VD1_IF0_LUMA_PSEL 0x1a60 266 #define VD1_IF0_CHROMA_PSEL 0x1a61 267 #define VD1_IF0_DUMMY_PIXEL 0x1a62 268 #define VD1_IF0_LUMA_FIFO_SIZE 0x1a63 269 #define VD1_IF0_RANGE_MAP_Y 0x1a6a 270 #define VD1_IF0_RANGE_MAP_CB 0x1a6b 271 #define VD1_IF0_RANGE_MAP_CR 0x1a6c 272 #define VD1_IF0_GEN_REG2 0x1a6d 273 #define VD1_IF0_PROT_CNTL 0x1a6e 274 #define VIU_VD1_FMT_CTRL 0x1a68 275 #define VIU_VD1_FMT_W 0x1a69 276 #define VD2_IF0_GEN_REG 0x1a70 277 #define VD2_IF0_CANVAS0 0x1a71 278 #define VD2_IF0_CANVAS1 0x1a72 279 #define VD2_IF0_LUMA_X0 0x1a73 280 #define VD2_IF0_LUMA_Y0 0x1a74 281 #define VD2_IF0_CHROMA_X0 0x1a75 282 #define VD2_IF0_CHROMA_Y0 0x1a76 283 #define VD2_IF0_LUMA_X1 0x1a77 284 #define VD2_IF0_LUMA_Y1 0x1a78 285 #define VD2_IF0_CHROMA_X1 0x1a79 286 #define VD2_IF0_CHROMA_Y1 0x1a7a 287 #define VD2_IF0_RPT_LOOP 0x1a7b 288 #define VD2_IF0_LUMA0_RPT_PAT 0x1a7c 289 #define VD2_IF0_CHROMA0_RPT_PAT 0x1a7d 290 #define VD2_IF0_LUMA1_RPT_PAT 0x1a7e 291 #define VD2_IF0_CHROMA1_RPT_PAT 0x1a7f 292 #define VD2_IF0_LUMA_PSEL 0x1a80 293 #define VD2_IF0_CHROMA_PSEL 0x1a81 294 #define VD2_IF0_DUMMY_PIXEL 0x1a82 295 #define VD2_IF0_LUMA_FIFO_SIZE 0x1a83 296 #define VD2_IF0_RANGE_MAP_Y 0x1a8a 297 #define VD2_IF0_RANGE_MAP_CB 0x1a8b 298 #define VD2_IF0_RANGE_MAP_CR 0x1a8c 299 #define VD2_IF0_GEN_REG2 0x1a8d 300 #define VD2_IF0_PROT_CNTL 0x1a8e 301 #define VIU_VD2_FMT_CTRL 0x1a88 302 #define VIU_VD2_FMT_W 0x1a89 303 304 /* VIU Matrix Registers */ 305 #define VIU_OSD1_MATRIX_CTRL 0x1a90 306 #define VIU_OSD1_MATRIX_COEF00_01 0x1a91 307 #define VIU_OSD1_MATRIX_COEF02_10 0x1a92 308 #define VIU_OSD1_MATRIX_COEF11_12 0x1a93 309 #define VIU_OSD1_MATRIX_COEF20_21 0x1a94 310 #define VIU_OSD1_MATRIX_COLMOD_COEF42 0x1a95 311 #define VIU_OSD1_MATRIX_OFFSET0_1 0x1a96 312 #define VIU_OSD1_MATRIX_OFFSET2 0x1a97 313 #define VIU_OSD1_MATRIX_PRE_OFFSET0_1 0x1a98 314 #define VIU_OSD1_MATRIX_PRE_OFFSET2 0x1a99 315 #define VIU_OSD1_MATRIX_COEF22_30 0x1a9d 316 #define VIU_OSD1_MATRIX_COEF31_32 0x1a9e 317 #define VIU_OSD1_MATRIX_COEF40_41 0x1a9f 318 #define VD1_IF0_GEN_REG3 0x1aa7 319 320 #define VIU_OSD_BLENDO_H_START_END 0x1aa9 321 #define VIU_OSD_BLENDO_V_START_END 0x1aaa 322 #define VIU_OSD_BLEND_GEN_CTRL0 0x1aab 323 #define VIU_OSD_BLEND_GEN_CTRL1 0x1aac 324 #define VIU_OSD_BLEND_DUMMY_DATA 0x1aad 325 #define VIU_OSD_BLEND_CURRENT_XY 0x1aae 326 327 #define VIU_OSD2_MATRIX_CTRL 0x1ab0 328 #define VIU_OSD2_MATRIX_COEF00_01 0x1ab1 329 #define VIU_OSD2_MATRIX_COEF02_10 0x1ab2 330 #define VIU_OSD2_MATRIX_COEF11_12 0x1ab3 331 #define VIU_OSD2_MATRIX_COEF20_21 0x1ab4 332 #define VIU_OSD2_MATRIX_COEF22 0x1ab5 333 #define VIU_OSD2_MATRIX_OFFSET0_1 0x1ab6 334 #define VIU_OSD2_MATRIX_OFFSET2 0x1ab7 335 #define VIU_OSD2_MATRIX_PRE_OFFSET0_1 0x1ab8 336 #define VIU_OSD2_MATRIX_PRE_OFFSET2 0x1ab9 337 #define VIU_OSD2_MATRIX_PROBE_COLOR 0x1aba 338 #define VIU_OSD2_MATRIX_HL_COLOR 0x1abb 339 #define VIU_OSD2_MATRIX_PROBE_POS 0x1abc 340 #define VIU_OSD1_EOTF_CTL 0x1ad4 341 #define VIU_OSD1_EOTF_COEF00_01 0x1ad5 342 #define VIU_OSD1_EOTF_COEF02_10 0x1ad6 343 #define VIU_OSD1_EOTF_COEF11_12 0x1ad7 344 #define VIU_OSD1_EOTF_COEF20_21 0x1ad8 345 #define VIU_OSD1_EOTF_COEF22_RS 0x1ad9 346 #define VIU_OSD1_EOTF_LUT_ADDR_PORT 0x1ada 347 #define VIU_OSD1_EOTF_LUT_DATA_PORT 0x1adb 348 #define VIU_OSD1_OETF_CTL 0x1adc 349 #define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add 350 #define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade 351 #define AFBC_ENABLE 0x1ae0 352 353 /* vpp */ 354 #define VPP_DUMMY_DATA 0x1d00 355 #define VPP_LINE_IN_LENGTH 0x1d01 356 #define VPP_PIC_IN_HEIGHT 0x1d02 357 #define VPP_SCALE_COEF_IDX 0x1d03 358 #define VPP_SCALE_HORIZONTAL_COEF BIT(8) 359 #define VPP_SCALE_COEF 0x1d04 360 #define VPP_VSC_REGION12_STARTP 0x1d05 361 #define VPP_VSC_REGION34_STARTP 0x1d06 362 #define VPP_VSC_REGION4_ENDP 0x1d07 363 #define VPP_VSC_START_PHASE_STEP 0x1d08 364 #define VPP_VSC_REGION0_PHASE_SLOPE 0x1d09 365 #define VPP_VSC_REGION1_PHASE_SLOPE 0x1d0a 366 #define VPP_VSC_REGION3_PHASE_SLOPE 0x1d0b 367 #define VPP_VSC_REGION4_PHASE_SLOPE 0x1d0c 368 #define VPP_VSC_PHASE_CTRL 0x1d0d 369 #define VPP_VSC_INI_PHASE 0x1d0e 370 #define VPP_HSC_REGION12_STARTP 0x1d10 371 #define VPP_HSC_REGION34_STARTP 0x1d11 372 #define VPP_HSC_REGION4_ENDP 0x1d12 373 #define VPP_HSC_START_PHASE_STEP 0x1d13 374 #define VPP_HSC_REGION0_PHASE_SLOPE 0x1d14 375 #define VPP_HSC_REGION1_PHASE_SLOPE 0x1d15 376 #define VPP_HSC_REGION3_PHASE_SLOPE 0x1d16 377 #define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17 378 #define VPP_HSC_PHASE_CTRL 0x1d18 379 #define VPP_SC_MISC 0x1d19 380 #define VPP_SC_VD_EN_ENABLE BIT(15) 381 #define VPP_SC_TOP_EN_ENABLE BIT(16) 382 #define VPP_SC_HSC_EN_ENABLE BIT(17) 383 #define VPP_SC_VSC_EN_ENABLE BIT(18) 384 #define VPP_VSC_BANK_LENGTH(length) (length & 0x7) 385 #define VPP_HSC_BANK_LENGTH(length) ((length & 0x7) << 8) 386 #define VPP_PREBLEND_VD1_H_START_END 0x1d1a 387 #define VPP_PREBLEND_VD1_V_START_END 0x1d1b 388 #define VPP_POSTBLEND_VD1_H_START_END 0x1d1c 389 #define VPP_POSTBLEND_VD1_V_START_END 0x1d1d 390 #define VPP_BLEND_VD2_H_START_END 0x1d1e 391 #define VPP_BLEND_VD2_V_START_END 0x1d1f 392 #define VPP_PREBLEND_H_SIZE 0x1d20 393 #define VPP_POSTBLEND_H_SIZE 0x1d21 394 #define VPP_HOLD_LINES 0x1d22 395 #define VPP_POSTBLEND_HOLD_LINES(lines) (lines & 0xf) 396 #define VPP_PREBLEND_HOLD_LINES(lines) ((lines & 0xf) << 8) 397 #define VPP_BLEND_ONECOLOR_CTRL 0x1d23 398 #define VPP_PREBLEND_CURRENT_XY 0x1d24 399 #define VPP_POSTBLEND_CURRENT_XY 0x1d25 400 #define VPP_MISC 0x1d26 401 #define VPP_PREBLEND_ENABLE BIT(6) 402 #define VPP_POSTBLEND_ENABLE BIT(7) 403 #define VPP_OSD2_ALPHA_PREMULT BIT(8) 404 #define VPP_OSD1_ALPHA_PREMULT BIT(9) 405 #define VPP_VD1_POSTBLEND BIT(10) 406 #define VPP_VD2_POSTBLEND BIT(11) 407 #define VPP_OSD1_POSTBLEND BIT(12) 408 #define VPP_OSD2_POSTBLEND BIT(13) 409 #define VPP_VD1_PREBLEND BIT(14) 410 #define VPP_VD2_PREBLEND BIT(15) 411 #define VPP_OSD1_PREBLEND BIT(16) 412 #define VPP_OSD2_PREBLEND BIT(17) 413 #define VPP_COLOR_MNG_ENABLE BIT(28) 414 #define VPP_OFIFO_SIZE 0x1d27 415 #define VPP_OFIFO_SIZE_MASK GENMASK(13, 0) 416 #define VPP_OFIFO_SIZE_DEFAULT (0xfff << 20 | 0x1000) 417 #define VPP_FIFO_STATUS 0x1d28 418 #define VPP_SMOKE_CTRL 0x1d29 419 #define VPP_SMOKE1_VAL 0x1d2a 420 #define VPP_SMOKE2_VAL 0x1d2b 421 #define VPP_SMOKE3_VAL 0x1d2c 422 #define VPP_SMOKE1_H_START_END 0x1d2d 423 #define VPP_SMOKE1_V_START_END 0x1d2e 424 #define VPP_SMOKE2_H_START_END 0x1d2f 425 #define VPP_SMOKE2_V_START_END 0x1d30 426 #define VPP_SMOKE3_H_START_END 0x1d31 427 #define VPP_SMOKE3_V_START_END 0x1d32 428 #define VPP_SCO_FIFO_CTRL 0x1d33 429 #define VPP_HSC_PHASE_CTRL1 0x1d34 430 #define VPP_HSC_INI_PAT_CTRL 0x1d35 431 #define VPP_VADJ_CTRL 0x1d40 432 #define VPP_MINUS_BLACK_LVL_VADJ1_ENABLE BIT(1) 433 434 #define VPP_VADJ1_Y 0x1d41 435 #define VPP_VADJ1_MA_MB 0x1d42 436 #define VPP_VADJ1_MC_MD 0x1d43 437 #define VPP_VADJ2_Y 0x1d44 438 #define VPP_VADJ2_MA_MB 0x1d45 439 #define VPP_VADJ2_MC_MD 0x1d46 440 #define VPP_HSHARP_CTRL 0x1d50 441 #define VPP_HSHARP_LUMA_THRESH01 0x1d51 442 #define VPP_HSHARP_LUMA_THRESH23 0x1d52 443 #define VPP_HSHARP_CHROMA_THRESH01 0x1d53 444 #define VPP_HSHARP_CHROMA_THRESH23 0x1d54 445 #define VPP_HSHARP_LUMA_GAIN 0x1d55 446 #define VPP_HSHARP_CHROMA_GAIN 0x1d56 447 #define VPP_MATRIX_PROBE_COLOR 0x1d5c 448 #define VPP_MATRIX_HL_COLOR 0x1d5d 449 #define VPP_MATRIX_PROBE_POS 0x1d5e 450 #define VPP_MATRIX_CTRL 0x1d5f 451 #define VPP_MATRIX_COEF00_01 0x1d60 452 #define VPP_MATRIX_COEF02_10 0x1d61 453 #define VPP_MATRIX_COEF11_12 0x1d62 454 #define VPP_MATRIX_COEF20_21 0x1d63 455 #define VPP_MATRIX_COEF22 0x1d64 456 #define VPP_MATRIX_OFFSET0_1 0x1d65 457 #define VPP_MATRIX_OFFSET2 0x1d66 458 #define VPP_MATRIX_PRE_OFFSET0_1 0x1d67 459 #define VPP_MATRIX_PRE_OFFSET2 0x1d68 460 #define VPP_DUMMY_DATA1 0x1d69 461 #define VPP_GAINOFF_CTRL0 0x1d6a 462 #define VPP_GAINOFF_CTRL1 0x1d6b 463 #define VPP_GAINOFF_CTRL2 0x1d6c 464 #define VPP_GAINOFF_CTRL3 0x1d6d 465 #define VPP_GAINOFF_CTRL4 0x1d6e 466 #define VPP_CHROMA_ADDR_PORT 0x1d70 467 #define VPP_CHROMA_DATA_PORT 0x1d71 468 #define VPP_GCLK_CTRL0 0x1d72 469 #define VPP_GCLK_CTRL1 0x1d73 470 #define VPP_SC_GCLK_CTRL 0x1d74 471 #define VPP_MISC1 0x1d76 472 #define VPP_BLACKEXT_CTRL 0x1d80 473 #define VPP_DNLP_CTRL_00 0x1d81 474 #define VPP_DNLP_CTRL_01 0x1d82 475 #define VPP_DNLP_CTRL_02 0x1d83 476 #define VPP_DNLP_CTRL_03 0x1d84 477 #define VPP_DNLP_CTRL_04 0x1d85 478 #define VPP_DNLP_CTRL_05 0x1d86 479 #define VPP_DNLP_CTRL_06 0x1d87 480 #define VPP_DNLP_CTRL_07 0x1d88 481 #define VPP_DNLP_CTRL_08 0x1d89 482 #define VPP_DNLP_CTRL_09 0x1d8a 483 #define VPP_DNLP_CTRL_10 0x1d8b 484 #define VPP_DNLP_CTRL_11 0x1d8c 485 #define VPP_DNLP_CTRL_12 0x1d8d 486 #define VPP_DNLP_CTRL_13 0x1d8e 487 #define VPP_DNLP_CTRL_14 0x1d8f 488 #define VPP_DNLP_CTRL_15 0x1d90 489 #define VPP_PEAKING_HGAIN 0x1d91 490 #define VPP_PEAKING_VGAIN 0x1d92 491 #define VPP_PEAKING_NLP_1 0x1d93 492 #define VPP_DOLBY_CTRL 0x1d93 493 #define VPP_PPS_DUMMY_DATA_MODE (1 << 17) 494 #define VPP_PEAKING_NLP_2 0x1d94 495 #define VPP_PEAKING_NLP_3 0x1d95 496 #define VPP_PEAKING_NLP_4 0x1d96 497 #define VPP_PEAKING_NLP_5 0x1d97 498 #define VPP_SHARP_LIMIT 0x1d98 499 #define VPP_VLTI_CTRL 0x1d99 500 #define VPP_HLTI_CTRL 0x1d9a 501 #define VPP_CTI_CTRL 0x1d9b 502 #define VPP_BLUE_STRETCH_1 0x1d9c 503 #define VPP_BLUE_STRETCH_2 0x1d9d 504 #define VPP_BLUE_STRETCH_3 0x1d9e 505 #define VPP_CCORING_CTRL 0x1da0 506 #define VPP_VE_ENABLE_CTRL 0x1da1 507 #define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x1da2 508 #define VPP_VE_DEMO_CENTER_BAR 0x1da3 509 #define VPP_VE_H_V_SIZE 0x1da4 510 #define VPP_VDO_MEAS_CTRL 0x1da8 511 #define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9 512 #define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa 513 #define VPP_INPUT_CTRL 0x1dab 514 #define VPP_CTI_CTRL2 0x1dac 515 #define VPP_PEAKING_SAT_THD1 0x1dad 516 #define VPP_PEAKING_SAT_THD2 0x1dae 517 #define VPP_PEAKING_SAT_THD3 0x1daf 518 #define VPP_PEAKING_SAT_THD4 0x1db0 519 #define VPP_PEAKING_SAT_THD5 0x1db1 520 #define VPP_PEAKING_SAT_THD6 0x1db2 521 #define VPP_PEAKING_SAT_THD7 0x1db3 522 #define VPP_PEAKING_SAT_THD8 0x1db4 523 #define VPP_PEAKING_SAT_THD9 0x1db5 524 #define VPP_PEAKING_GAIN_ADD1 0x1db6 525 #define VPP_PEAKING_GAIN_ADD2 0x1db7 526 #define VPP_PEAKING_DNLP 0x1db8 527 #define VPP_SHARP_DEMO_WIN_CTRL1 0x1db9 528 #define VPP_SHARP_DEMO_WIN_CTRL2 0x1dba 529 #define VPP_FRONT_HLTI_CTRL 0x1dbb 530 #define VPP_FRONT_CTI_CTRL 0x1dbc 531 #define VPP_FRONT_CTI_CTRL2 0x1dbd 532 #define VPP_OSD_VSC_PHASE_STEP 0x1dc0 533 #define VPP_OSD_VSC_INI_PHASE 0x1dc1 534 #define VPP_OSD_VSC_CTRL0 0x1dc2 535 #define VPP_OSD_HSC_PHASE_STEP 0x1dc3 536 #define VPP_OSD_HSC_INI_PHASE 0x1dc4 537 #define VPP_OSD_HSC_CTRL0 0x1dc5 538 #define VPP_OSD_HSC_INI_PAT_CTRL 0x1dc6 539 #define VPP_OSD_SC_DUMMY_DATA 0x1dc7 540 #define VPP_OSD_SC_CTRL0 0x1dc8 541 #define VPP_OSD_SCI_WH_M1 0x1dc9 542 #define VPP_OSD_SCO_H_START_END 0x1dca 543 #define VPP_OSD_SCO_V_START_END 0x1dcb 544 #define VPP_OSD_SCALE_COEF_IDX 0x1dcc 545 #define VPP_OSD_SCALE_COEF 0x1dcd 546 #define VPP_INT_LINE_NUM 0x1dce 547 548 #define VPP_WRAP_OSD1_MATRIX_COEF00_01 0x3d60 549 #define VPP_WRAP_OSD1_MATRIX_COEF02_10 0x3d61 550 #define VPP_WRAP_OSD1_MATRIX_COEF11_12 0x3d62 551 #define VPP_WRAP_OSD1_MATRIX_COEF20_21 0x3d63 552 #define VPP_WRAP_OSD1_MATRIX_COEF22 0x3d64 553 #define VPP_WRAP_OSD1_MATRIX_COEF13_14 0x3d65 554 #define VPP_WRAP_OSD1_MATRIX_COEF23_24 0x3d66 555 #define VPP_WRAP_OSD1_MATRIX_COEF15_25 0x3d67 556 #define VPP_WRAP_OSD1_MATRIX_CLIP 0x3d68 557 #define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 0x3d69 558 #define VPP_WRAP_OSD1_MATRIX_OFFSET2 0x3d6a 559 #define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 0x3d6b 560 #define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 0x3d6c 561 #define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d 562 563 #define VPP_WRAP_OSD2_MATRIX_COEF00_01 0x3d70 564 #define VPP_WRAP_OSD2_MATRIX_COEF02_10 0x3d71 565 #define VPP_WRAP_OSD2_MATRIX_COEF11_12 0x3d72 566 #define VPP_WRAP_OSD2_MATRIX_COEF20_21 0x3d73 567 #define VPP_WRAP_OSD2_MATRIX_COEF22 0x3d74 568 #define VPP_WRAP_OSD2_MATRIX_COEF13_14 0x3d75 569 #define VPP_WRAP_OSD2_MATRIX_COEF23_24 0x3d76 570 #define VPP_WRAP_OSD2_MATRIX_COEF15_25 0x3d77 571 #define VPP_WRAP_OSD2_MATRIX_CLIP 0x3d78 572 #define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 0x3d79 573 #define VPP_WRAP_OSD2_MATRIX_OFFSET2 0x3d7a 574 #define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 0x3d7b 575 #define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 0x3d7c 576 #define VPP_WRAP_OSD2_MATRIX_EN_CTRL 0x3d7d 577 578 #define VPP_WRAP_OSD3_MATRIX_COEF00_01 0x3db0 579 #define VPP_WRAP_OSD3_MATRIX_COEF02_10 0x3db1 580 #define VPP_WRAP_OSD3_MATRIX_COEF11_12 0x3db2 581 #define VPP_WRAP_OSD3_MATRIX_COEF20_21 0x3db3 582 #define VPP_WRAP_OSD3_MATRIX_COEF22 0x3db4 583 #define VPP_WRAP_OSD3_MATRIX_COEF13_14 0x3db5 584 #define VPP_WRAP_OSD3_MATRIX_COEF23_24 0x3db6 585 #define VPP_WRAP_OSD3_MATRIX_COEF15_25 0x3db7 586 #define VPP_WRAP_OSD3_MATRIX_CLIP 0x3db8 587 #define VPP_WRAP_OSD3_MATRIX_OFFSET0_1 0x3db9 588 #define VPP_WRAP_OSD3_MATRIX_OFFSET2 0x3dba 589 #define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 0x3dbb 590 #define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc 591 #define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd 592 593 /* osd2 scaler */ 594 #define OSD2_VSC_PHASE_STEP 0x3d00 595 #define OSD2_VSC_INI_PHASE 0x3d01 596 #define OSD2_VSC_CTRL0 0x3d02 597 #define OSD2_HSC_PHASE_STEP 0x3d03 598 #define OSD2_HSC_INI_PHASE 0x3d04 599 #define OSD2_HSC_CTRL0 0x3d05 600 #define OSD2_HSC_INI_PAT_CTRL 0x3d06 601 #define OSD2_SC_DUMMY_DATA 0x3d07 602 #define OSD2_SC_CTRL0 0x3d08 603 #define OSD2_SCI_WH_M1 0x3d09 604 #define OSD2_SCO_H_START_END 0x3d0a 605 #define OSD2_SCO_V_START_END 0x3d0b 606 #define OSD2_SCALE_COEF_IDX 0x3d18 607 #define OSD2_SCALE_COEF 0x3d19 608 609 /* osd34 scaler */ 610 #define OSD34_SCALE_COEF_IDX 0x3d1e 611 #define OSD34_SCALE_COEF 0x3d1f 612 #define OSD34_VSC_PHASE_STEP 0x3d20 613 #define OSD34_VSC_INI_PHASE 0x3d21 614 #define OSD34_VSC_CTRL0 0x3d22 615 #define OSD34_HSC_PHASE_STEP 0x3d23 616 #define OSD34_HSC_INI_PHASE 0x3d24 617 #define OSD34_HSC_CTRL0 0x3d25 618 #define OSD34_HSC_INI_PAT_CTRL 0x3d26 619 #define OSD34_SC_DUMMY_DATA 0x3d27 620 #define OSD34_SC_CTRL0 0x3d28 621 #define OSD34_SCI_WH_M1 0x3d29 622 #define OSD34_SCO_H_START_END 0x3d2a 623 #define OSD34_SCO_V_START_END 0x3d2b 624 625 /* viu2 */ 626 #define VIU2_ADDR_START 0x1e00 627 #define VIU2_ADDR_END 0x1eff 628 #define VIU2_SW_RESET 0x1e01 629 #define VIU2_OSD1_CTRL_STAT 0x1e10 630 #define VIU2_OSD1_CTRL_STAT2 0x1e2d 631 #define VIU2_OSD1_COLOR_ADDR 0x1e11 632 #define VIU2_OSD1_COLOR 0x1e12 633 #define VIU2_OSD1_TCOLOR_AG0 0x1e17 634 #define VIU2_OSD1_TCOLOR_AG1 0x1e18 635 #define VIU2_OSD1_TCOLOR_AG2 0x1e19 636 #define VIU2_OSD1_TCOLOR_AG3 0x1e1a 637 #define VIU2_OSD1_BLK0_CFG_W0 0x1e1b 638 #define VIU2_OSD1_BLK1_CFG_W0 0x1e1f 639 #define VIU2_OSD1_BLK2_CFG_W0 0x1e23 640 #define VIU2_OSD1_BLK3_CFG_W0 0x1e27 641 #define VIU2_OSD1_BLK0_CFG_W1 0x1e1c 642 #define VIU2_OSD1_BLK1_CFG_W1 0x1e20 643 #define VIU2_OSD1_BLK2_CFG_W1 0x1e24 644 #define VIU2_OSD1_BLK3_CFG_W1 0x1e28 645 #define VIU2_OSD1_BLK0_CFG_W2 0x1e1d 646 #define VIU2_OSD1_BLK1_CFG_W2 0x1e21 647 #define VIU2_OSD1_BLK2_CFG_W2 0x1e25 648 #define VIU2_OSD1_BLK3_CFG_W2 0x1e29 649 #define VIU2_OSD1_BLK0_CFG_W3 0x1e1e 650 #define VIU2_OSD1_BLK1_CFG_W3 0x1e22 651 #define VIU2_OSD1_BLK2_CFG_W3 0x1e26 652 #define VIU2_OSD1_BLK3_CFG_W3 0x1e2a 653 #define VIU2_OSD1_BLK0_CFG_W4 0x1e13 654 #define VIU2_OSD1_BLK1_CFG_W4 0x1e14 655 #define VIU2_OSD1_BLK2_CFG_W4 0x1e15 656 #define VIU2_OSD1_BLK3_CFG_W4 0x1e16 657 #define VIU2_OSD1_FIFO_CTRL_STAT 0x1e2b 658 #define VIU2_OSD1_TEST_RDDATA 0x1e2c 659 #define VIU2_OSD1_PROT_CTRL 0x1e2e 660 #define VIU2_OSD2_CTRL_STAT 0x1e30 661 #define VIU2_OSD2_CTRL_STAT2 0x1e4d 662 #define VIU2_OSD2_COLOR_ADDR 0x1e31 663 #define VIU2_OSD2_COLOR 0x1e32 664 #define VIU2_OSD2_HL1_H_START_END 0x1e33 665 #define VIU2_OSD2_HL1_V_START_END 0x1e34 666 #define VIU2_OSD2_HL2_H_START_END 0x1e35 667 #define VIU2_OSD2_HL2_V_START_END 0x1e36 668 #define VIU2_OSD2_TCOLOR_AG0 0x1e37 669 #define VIU2_OSD2_TCOLOR_AG1 0x1e38 670 #define VIU2_OSD2_TCOLOR_AG2 0x1e39 671 #define VIU2_OSD2_TCOLOR_AG3 0x1e3a 672 #define VIU2_OSD2_BLK0_CFG_W0 0x1e3b 673 #define VIU2_OSD2_BLK1_CFG_W0 0x1e3f 674 #define VIU2_OSD2_BLK2_CFG_W0 0x1e43 675 #define VIU2_OSD2_BLK3_CFG_W0 0x1e47 676 #define VIU2_OSD2_BLK0_CFG_W1 0x1e3c 677 #define VIU2_OSD2_BLK1_CFG_W1 0x1e40 678 #define VIU2_OSD2_BLK2_CFG_W1 0x1e44 679 #define VIU2_OSD2_BLK3_CFG_W1 0x1e48 680 #define VIU2_OSD2_BLK0_CFG_W2 0x1e3d 681 #define VIU2_OSD2_BLK1_CFG_W2 0x1e41 682 #define VIU2_OSD2_BLK2_CFG_W2 0x1e45 683 #define VIU2_OSD2_BLK3_CFG_W2 0x1e49 684 #define VIU2_OSD2_BLK0_CFG_W3 0x1e3e 685 #define VIU2_OSD2_BLK1_CFG_W3 0x1e42 686 #define VIU2_OSD2_BLK2_CFG_W3 0x1e46 687 #define VIU2_OSD2_BLK3_CFG_W3 0x1e4a 688 #define VIU2_OSD2_BLK0_CFG_W4 0x1e64 689 #define VIU2_OSD2_BLK1_CFG_W4 0x1e65 690 #define VIU2_OSD2_BLK2_CFG_W4 0x1e66 691 #define VIU2_OSD2_BLK3_CFG_W4 0x1e67 692 #define VIU2_OSD2_FIFO_CTRL_STAT 0x1e4b 693 #define VIU2_OSD2_TEST_RDDATA 0x1e4c 694 #define VIU2_OSD2_PROT_CTRL 0x1e4e 695 #define VIU2_VD1_IF0_GEN_REG 0x1e50 696 #define VIU2_VD1_IF0_CANVAS0 0x1e51 697 #define VIU2_VD1_IF0_CANVAS1 0x1e52 698 #define VIU2_VD1_IF0_LUMA_X0 0x1e53 699 #define VIU2_VD1_IF0_LUMA_Y0 0x1e54 700 #define VIU2_VD1_IF0_CHROMA_X0 0x1e55 701 #define VIU2_VD1_IF0_CHROMA_Y0 0x1e56 702 #define VIU2_VD1_IF0_LUMA_X1 0x1e57 703 #define VIU2_VD1_IF0_LUMA_Y1 0x1e58 704 #define VIU2_VD1_IF0_CHROMA_X1 0x1e59 705 #define VIU2_VD1_IF0_CHROMA_Y1 0x1e5a 706 #define VIU2_VD1_IF0_RPT_LOOP 0x1e5b 707 #define VIU2_VD1_IF0_LUMA0_RPT_PAT 0x1e5c 708 #define VIU2_VD1_IF0_CHROMA0_RPT_PAT 0x1e5d 709 #define VIU2_VD1_IF0_LUMA1_RPT_PAT 0x1e5e 710 #define VIU2_VD1_IF0_CHROMA1_RPT_PAT 0x1e5f 711 #define VIU2_VD1_IF0_LUMA_PSEL 0x1e60 712 #define VIU2_VD1_IF0_CHROMA_PSEL 0x1e61 713 #define VIU2_VD1_IF0_DUMMY_PIXEL 0x1e62 714 #define VIU2_VD1_IF0_LUMA_FIFO_SIZE 0x1e63 715 #define VIU2_VD1_IF0_RANGE_MAP_Y 0x1e6a 716 #define VIU2_VD1_IF0_RANGE_MAP_CB 0x1e6b 717 #define VIU2_VD1_IF0_RANGE_MAP_CR 0x1e6c 718 #define VIU2_VD1_IF0_GEN_REG2 0x1e6d 719 #define VIU2_VD1_IF0_PROT_CNTL 0x1e6e 720 #define VIU2_VD1_FMT_CTRL 0x1e68 721 #define VIU2_VD1_FMT_W 0x1e69 722 723 /* encode */ 724 #define ENCP_VFIFO2VD_CTL 0x1b58 725 #define ENCP_VFIFO2VD_PIXEL_START 0x1b59 726 #define ENCP_VFIFO2VD_PIXEL_END 0x1b5a 727 #define ENCP_VFIFO2VD_LINE_TOP_START 0x1b5b 728 #define ENCP_VFIFO2VD_LINE_TOP_END 0x1b5c 729 #define ENCP_VFIFO2VD_LINE_BOT_START 0x1b5d 730 #define ENCP_VFIFO2VD_LINE_BOT_END 0x1b5e 731 #define VENC_SYNC_ROUTE 0x1b60 732 #define VENC_VIDEO_EXSRC 0x1b61 733 #define VENC_DVI_SETTING 0x1b62 734 #define VENC_C656_CTRL 0x1b63 735 #define VENC_UPSAMPLE_CTRL0 0x1b64 736 #define VENC_UPSAMPLE_CTRL1 0x1b65 737 #define VENC_UPSAMPLE_CTRL2 0x1b66 738 #define VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO BIT(0) 739 #define VENC_UPSAMPLE_CTRL_F1_EN BIT(5) 740 #define VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN BIT(6) 741 #define VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA (0x0 << 12) 742 #define VENC_UPSAMPLE_CTRL_CVBS (0x1 << 12) 743 #define VENC_UPSAMPLE_CTRL_S_VIDEO_LUMA (0x2 << 12) 744 #define VENC_UPSAMPLE_CTRL_S_VIDEO_CHROMA (0x3 << 12) 745 #define VENC_UPSAMPLE_CTRL_INTERLACE_PB (0x4 << 12) 746 #define VENC_UPSAMPLE_CTRL_INTERLACE_PR (0x5 << 12) 747 #define VENC_UPSAMPLE_CTRL_INTERLACE_R (0x6 << 12) 748 #define VENC_UPSAMPLE_CTRL_INTERLACE_G (0x7 << 12) 749 #define VENC_UPSAMPLE_CTRL_INTERLACE_B (0x8 << 12) 750 #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_Y (0x9 << 12) 751 #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PB (0xa << 12) 752 #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PR (0xb << 12) 753 #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_R (0xc << 12) 754 #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_G (0xd << 12) 755 #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_B (0xe << 12) 756 #define VENC_UPSAMPLE_CTRL_VDAC_TEST_VALUE (0xf << 12) 757 #define TCON_INVERT_CTL 0x1b67 758 #define VENC_VIDEO_PROG_MODE 0x1b68 759 #define VENC_ENCI_LINE 0x1b69 760 #define VENC_ENCI_PIXEL 0x1b6a 761 #define VENC_ENCP_LINE 0x1b6b 762 #define VENC_ENCP_PIXEL 0x1b6c 763 #define VENC_STATA 0x1b6d 764 #define VENC_INTCTRL 0x1b6e 765 #define VENC_INTCTRL_ENCI_LNRST_INT_EN BIT(1) 766 #define VENC_INTFLAG 0x1b6f 767 #define VENC_VIDEO_TST_EN 0x1b70 768 #define VENC_VIDEO_TST_MDSEL 0x1b71 769 #define VENC_VIDEO_TST_Y 0x1b72 770 #define VENC_VIDEO_TST_CB 0x1b73 771 #define VENC_VIDEO_TST_CR 0x1b74 772 #define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75 773 #define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76 774 #define VENC_VIDEO_TST_VDCNT_STSET 0x1b77 775 #define VENC_VDAC_DACSEL0 0x1b78 776 #define VENC_VDAC_SEL_ATV_DMD BIT(5) 777 #define VENC_VDAC_DACSEL1 0x1b79 778 #define VENC_VDAC_DACSEL2 0x1b7a 779 #define VENC_VDAC_DACSEL3 0x1b7b 780 #define VENC_VDAC_DACSEL4 0x1b7c 781 #define VENC_VDAC_DACSEL5 0x1b7d 782 #define VENC_VDAC_SETTING 0x1b7e 783 #define VENC_VDAC_TST_VAL 0x1b7f 784 #define VENC_VDAC_DAC0_GAINCTRL 0x1bf0 785 #define VENC_VDAC_DAC0_OFFSET 0x1bf1 786 #define VENC_VDAC_DAC1_GAINCTRL 0x1bf2 787 #define VENC_VDAC_DAC1_OFFSET 0x1bf3 788 #define VENC_VDAC_DAC2_GAINCTRL 0x1bf4 789 #define VENC_VDAC_DAC2_OFFSET 0x1bf5 790 #define VENC_VDAC_DAC3_GAINCTRL 0x1bf6 791 #define VENC_VDAC_DAC3_OFFSET 0x1bf7 792 #define VENC_VDAC_DAC4_GAINCTRL 0x1bf8 793 #define VENC_VDAC_DAC4_OFFSET 0x1bf9 794 #define VENC_VDAC_DAC5_GAINCTRL 0x1bfa 795 #define VENC_VDAC_DAC5_OFFSET 0x1bfb 796 #define VENC_VDAC_FIFO_CTRL 0x1bfc 797 #define VENC_VDAC_FIFO_EN_ENCI_ENABLE BIT(13) 798 #define ENCL_TCON_INVERT_CTL 0x1bfd 799 #define ENCP_VIDEO_EN 0x1b80 800 #define ENCP_VIDEO_SYNC_MODE 0x1b81 801 #define ENCP_MACV_EN 0x1b82 802 #define ENCP_VIDEO_Y_SCL 0x1b83 803 #define ENCP_VIDEO_PB_SCL 0x1b84 804 #define ENCP_VIDEO_PR_SCL 0x1b85 805 #define ENCP_VIDEO_SYNC_SCL 0x1b86 806 #define ENCP_VIDEO_MACV_SCL 0x1b87 807 #define ENCP_VIDEO_Y_OFFST 0x1b88 808 #define ENCP_VIDEO_PB_OFFST 0x1b89 809 #define ENCP_VIDEO_PR_OFFST 0x1b8a 810 #define ENCP_VIDEO_SYNC_OFFST 0x1b8b 811 #define ENCP_VIDEO_MACV_OFFST 0x1b8c 812 #define ENCP_VIDEO_MODE 0x1b8d 813 #define ENCP_VIDEO_MODE_DE_V_HIGH BIT(14) 814 #define ENCP_VIDEO_MODE_ADV 0x1b8e 815 #define ENCP_DBG_PX_RST 0x1b90 816 #define ENCP_DBG_LN_RST 0x1b91 817 #define ENCP_DBG_PX_INT 0x1b92 818 #define ENCP_DBG_LN_INT 0x1b93 819 #define ENCP_VIDEO_YFP1_HTIME 0x1b94 820 #define ENCP_VIDEO_YFP2_HTIME 0x1b95 821 #define ENCP_VIDEO_YC_DLY 0x1b96 822 #define ENCP_VIDEO_MAX_PXCNT 0x1b97 823 #define ENCP_VIDEO_HSPULS_BEGIN 0x1b98 824 #define ENCP_VIDEO_HSPULS_END 0x1b99 825 #define ENCP_VIDEO_HSPULS_SWITCH 0x1b9a 826 #define ENCP_VIDEO_VSPULS_BEGIN 0x1b9b 827 #define ENCP_VIDEO_VSPULS_END 0x1b9c 828 #define ENCP_VIDEO_VSPULS_BLINE 0x1b9d 829 #define ENCP_VIDEO_VSPULS_ELINE 0x1b9e 830 #define ENCP_VIDEO_EQPULS_BEGIN 0x1b9f 831 #define ENCP_VIDEO_EQPULS_END 0x1ba0 832 #define ENCP_VIDEO_EQPULS_BLINE 0x1ba1 833 #define ENCP_VIDEO_EQPULS_ELINE 0x1ba2 834 #define ENCP_VIDEO_HAVON_END 0x1ba3 835 #define ENCP_VIDEO_HAVON_BEGIN 0x1ba4 836 #define ENCP_VIDEO_VAVON_ELINE 0x1baf 837 #define ENCP_VIDEO_VAVON_BLINE 0x1ba6 838 #define ENCP_VIDEO_HSO_BEGIN 0x1ba7 839 #define ENCP_VIDEO_HSO_END 0x1ba8 840 #define ENCP_VIDEO_VSO_BEGIN 0x1ba9 841 #define ENCP_VIDEO_VSO_END 0x1baa 842 #define ENCP_VIDEO_VSO_BLINE 0x1bab 843 #define ENCP_VIDEO_VSO_ELINE 0x1bac 844 #define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad 845 #define ENCP_VIDEO_MAX_LNCNT 0x1bae 846 #define ENCP_VIDEO_SY_VAL 0x1bb0 847 #define ENCP_VIDEO_SY2_VAL 0x1bb1 848 #define ENCP_VIDEO_BLANKY_VAL 0x1bb2 849 #define ENCP_VIDEO_BLANKPB_VAL 0x1bb3 850 #define ENCP_VIDEO_BLANKPR_VAL 0x1bb4 851 #define ENCP_VIDEO_HOFFST 0x1bb5 852 #define ENCP_VIDEO_VOFFST 0x1bb6 853 #define ENCP_VIDEO_RGB_CTRL 0x1bb7 854 #define ENCP_VIDEO_FILT_CTRL 0x1bb8 855 #define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9 856 #define ENCP_VIDEO_OFLD_VOAV_OFST 0x1bba 857 #define ENCP_VIDEO_MATRIX_CB 0x1bbb 858 #define ENCP_VIDEO_MATRIX_CR 0x1bbc 859 #define ENCP_VIDEO_RGBIN_CTRL 0x1bbd 860 #define ENCP_MACV_BLANKY_VAL 0x1bc0 861 #define ENCP_MACV_MAXY_VAL 0x1bc1 862 #define ENCP_MACV_1ST_PSSYNC_STRT 0x1bc2 863 #define ENCP_MACV_PSSYNC_STRT 0x1bc3 864 #define ENCP_MACV_AGC_STRT 0x1bc4 865 #define ENCP_MACV_AGC_END 0x1bc5 866 #define ENCP_MACV_WAVE_END 0x1bc6 867 #define ENCP_MACV_STRTLINE 0x1bc7 868 #define ENCP_MACV_ENDLINE 0x1bc8 869 #define ENCP_MACV_TS_CNT_MAX_L 0x1bc9 870 #define ENCP_MACV_TS_CNT_MAX_H 0x1bca 871 #define ENCP_MACV_TIME_DOWN 0x1bcb 872 #define ENCP_MACV_TIME_LO 0x1bcc 873 #define ENCP_MACV_TIME_UP 0x1bcd 874 #define ENCP_MACV_TIME_RST 0x1bce 875 #define ENCP_VBI_CTRL 0x1bd0 876 #define ENCP_VBI_SETTING 0x1bd1 877 #define ENCP_VBI_BEGIN 0x1bd2 878 #define ENCP_VBI_WIDTH 0x1bd3 879 #define ENCP_VBI_HVAL 0x1bd4 880 #define ENCP_VBI_DATA0 0x1bd5 881 #define ENCP_VBI_DATA1 0x1bd6 882 #define C656_HS_ST 0x1be0 883 #define C656_HS_ED 0x1be1 884 #define C656_VS_LNST_E 0x1be2 885 #define C656_VS_LNST_O 0x1be3 886 #define C656_VS_LNED_E 0x1be4 887 #define C656_VS_LNED_O 0x1be5 888 #define C656_FS_LNST 0x1be6 889 #define C656_FS_LNED 0x1be7 890 #define ENCI_VIDEO_MODE 0x1b00 891 #define ENCI_VIDEO_MODE_ADV 0x1b01 892 #define ENCI_VIDEO_MODE_ADV_DMXMD(val) (val & 0x3) 893 #define ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 BIT(2) 894 #define ENCI_VIDEO_MODE_ADV_YBW_MEDIUM (0 << 4) 895 #define ENCI_VIDEO_MODE_ADV_YBW_LOW (0x1 << 4) 896 #define ENCI_VIDEO_MODE_ADV_YBW_HIGH (0x2 << 4) 897 #define ENCI_VIDEO_FSC_ADJ 0x1b02 898 #define ENCI_VIDEO_BRIGHT 0x1b03 899 #define ENCI_VIDEO_CONT 0x1b04 900 #define ENCI_VIDEO_SAT 0x1b05 901 #define ENCI_VIDEO_HUE 0x1b06 902 #define ENCI_VIDEO_SCH 0x1b07 903 #define ENCI_SYNC_MODE 0x1b08 904 #define ENCI_SYNC_CTRL 0x1b09 905 #define ENCI_SYNC_HSO_BEGIN 0x1b0a 906 #define ENCI_SYNC_HSO_END 0x1b0b 907 #define ENCI_SYNC_VSO_EVN 0x1b0c 908 #define ENCI_SYNC_VSO_ODD 0x1b0d 909 #define ENCI_SYNC_VSO_EVNLN 0x1b0e 910 #define ENCI_SYNC_VSO_ODDLN 0x1b0f 911 #define ENCI_SYNC_HOFFST 0x1b10 912 #define ENCI_SYNC_VOFFST 0x1b11 913 #define ENCI_SYNC_ADJ 0x1b12 914 #define ENCI_RGB_SETTING 0x1b13 915 #define ENCI_DE_H_BEGIN 0x1b16 916 #define ENCI_DE_H_END 0x1b17 917 #define ENCI_DE_V_BEGIN_EVEN 0x1b18 918 #define ENCI_DE_V_END_EVEN 0x1b19 919 #define ENCI_DE_V_BEGIN_ODD 0x1b1a 920 #define ENCI_DE_V_END_ODD 0x1b1b 921 #define ENCI_VBI_SETTING 0x1b20 922 #define ENCI_VBI_CCDT_EVN 0x1b21 923 #define ENCI_VBI_CCDT_ODD 0x1b22 924 #define ENCI_VBI_CC525_LN 0x1b23 925 #define ENCI_VBI_CC625_LN 0x1b24 926 #define ENCI_VBI_WSSDT 0x1b25 927 #define ENCI_VBI_WSS_LN 0x1b26 928 #define ENCI_VBI_CGMSDT_L 0x1b27 929 #define ENCI_VBI_CGMSDT_H 0x1b28 930 #define ENCI_VBI_CGMS_LN 0x1b29 931 #define ENCI_VBI_TTX_HTIME 0x1b2a 932 #define ENCI_VBI_TTX_LN 0x1b2b 933 #define ENCI_VBI_TTXDT0 0x1b2c 934 #define ENCI_VBI_TTXDT1 0x1b2d 935 #define ENCI_VBI_TTXDT2 0x1b2e 936 #define ENCI_VBI_TTXDT3 0x1b2f 937 #define ENCI_MACV_N0 0x1b30 938 #define ENCI_MACV_N1 0x1b31 939 #define ENCI_MACV_N2 0x1b32 940 #define ENCI_MACV_N3 0x1b33 941 #define ENCI_MACV_N4 0x1b34 942 #define ENCI_MACV_N5 0x1b35 943 #define ENCI_MACV_N6 0x1b36 944 #define ENCI_MACV_N7 0x1b37 945 #define ENCI_MACV_N8 0x1b38 946 #define ENCI_MACV_N9 0x1b39 947 #define ENCI_MACV_N10 0x1b3a 948 #define ENCI_MACV_N11 0x1b3b 949 #define ENCI_MACV_N12 0x1b3c 950 #define ENCI_MACV_N13 0x1b3d 951 #define ENCI_MACV_N14 0x1b3e 952 #define ENCI_MACV_N15 0x1b3f 953 #define ENCI_MACV_N16 0x1b40 954 #define ENCI_MACV_N17 0x1b41 955 #define ENCI_MACV_N18 0x1b42 956 #define ENCI_MACV_N19 0x1b43 957 #define ENCI_MACV_N20 0x1b44 958 #define ENCI_MACV_N21 0x1b45 959 #define ENCI_MACV_N22 0x1b46 960 #define ENCI_DBG_PX_RST 0x1b48 961 #define ENCI_DBG_FLDLN_RST 0x1b49 962 #define ENCI_DBG_PX_INT 0x1b4a 963 #define ENCI_DBG_FLDLN_INT 0x1b4b 964 #define ENCI_DBG_MAXPX 0x1b4c 965 #define ENCI_DBG_MAXLN 0x1b4d 966 #define ENCI_MACV_MAX_AMP 0x1b50 967 #define ENCI_MACV_MAX_AMP_ENABLE_CHANGE BIT(15) 968 #define ENCI_MACV_MAX_AMP_VAL(val) (val & 0x83ff) 969 #define ENCI_MACV_PULSE_LO 0x1b51 970 #define ENCI_MACV_PULSE_HI 0x1b52 971 #define ENCI_MACV_BKP_MAX 0x1b53 972 #define ENCI_CFILT_CTRL 0x1b54 973 #define ENCI_CFILT_CMPT_SEL_HIGH BIT(1) 974 #define ENCI_CFILT7 0x1b55 975 #define ENCI_YC_DELAY 0x1b56 976 #define ENCI_VIDEO_EN 0x1b57 977 #define ENCI_VIDEO_EN_ENABLE BIT(0) 978 #define ENCI_DVI_HSO_BEGIN 0x1c00 979 #define ENCI_DVI_HSO_END 0x1c01 980 #define ENCI_DVI_VSO_BLINE_EVN 0x1c02 981 #define ENCI_DVI_VSO_BLINE_ODD 0x1c03 982 #define ENCI_DVI_VSO_ELINE_EVN 0x1c04 983 #define ENCI_DVI_VSO_ELINE_ODD 0x1c05 984 #define ENCI_DVI_VSO_BEGIN_EVN 0x1c06 985 #define ENCI_DVI_VSO_BEGIN_ODD 0x1c07 986 #define ENCI_DVI_VSO_END_EVN 0x1c08 987 #define ENCI_DVI_VSO_END_ODD 0x1c09 988 #define ENCI_CFILT_CTRL2 0x1c0a 989 #define ENCI_CFILT_CMPT_CR_DLY(delay) (delay & 0xf) 990 #define ENCI_CFILT_CMPT_CB_DLY(delay) ((delay & 0xf) << 4) 991 #define ENCI_CFILT_CVBS_CR_DLY(delay) ((delay & 0xf) << 8) 992 #define ENCI_CFILT_CVBS_CB_DLY(delay) ((delay & 0xf) << 12) 993 #define ENCI_DACSEL_0 0x1c0b 994 #define ENCI_DACSEL_1 0x1c0c 995 #define ENCP_DACSEL_0 0x1c0d 996 #define ENCP_DACSEL_1 0x1c0e 997 #define ENCP_MAX_LINE_SWITCH_POINT 0x1c0f 998 #define ENCI_TST_EN 0x1c10 999 #define ENCI_TST_MDSEL 0x1c11 1000 #define ENCI_TST_Y 0x1c12 1001 #define ENCI_TST_CB 0x1c13 1002 #define ENCI_TST_CR 0x1c14 1003 #define ENCI_TST_CLRBAR_STRT 0x1c15 1004 #define ENCI_TST_CLRBAR_WIDTH 0x1c16 1005 #define ENCI_TST_VDCNT_STSET 0x1c17 1006 #define ENCI_VFIFO2VD_CTL 0x1c18 1007 #define ENCI_VFIFO2VD_CTL_ENABLE BIT(0) 1008 #define ENCI_VFIFO2VD_CTL_VD_SEL(val) ((val & 0xff) << 8) 1009 #define ENCI_VFIFO2VD_PIXEL_START 0x1c19 1010 #define ENCI_VFIFO2VD_PIXEL_END 0x1c1a 1011 #define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b 1012 #define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c 1013 #define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d 1014 #define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e 1015 #define ENCI_VFIFO2VD_CTL2 0x1c1f 1016 #define ENCT_VFIFO2VD_CTL 0x1c20 1017 #define ENCT_VFIFO2VD_PIXEL_START 0x1c21 1018 #define ENCT_VFIFO2VD_PIXEL_END 0x1c22 1019 #define ENCT_VFIFO2VD_LINE_TOP_START 0x1c23 1020 #define ENCT_VFIFO2VD_LINE_TOP_END 0x1c24 1021 #define ENCT_VFIFO2VD_LINE_BOT_START 0x1c25 1022 #define ENCT_VFIFO2VD_LINE_BOT_END 0x1c26 1023 #define ENCT_VFIFO2VD_CTL2 0x1c27 1024 #define ENCT_TST_EN 0x1c28 1025 #define ENCT_TST_MDSEL 0x1c29 1026 #define ENCT_TST_Y 0x1c2a 1027 #define ENCT_TST_CB 0x1c2b 1028 #define ENCT_TST_CR 0x1c2c 1029 #define ENCT_TST_CLRBAR_STRT 0x1c2d 1030 #define ENCT_TST_CLRBAR_WIDTH 0x1c2e 1031 #define ENCT_TST_VDCNT_STSET 0x1c2f 1032 #define ENCP_DVI_HSO_BEGIN 0x1c30 1033 #define ENCP_DVI_HSO_END 0x1c31 1034 #define ENCP_DVI_VSO_BLINE_EVN 0x1c32 1035 #define ENCP_DVI_VSO_BLINE_ODD 0x1c33 1036 #define ENCP_DVI_VSO_ELINE_EVN 0x1c34 1037 #define ENCP_DVI_VSO_ELINE_ODD 0x1c35 1038 #define ENCP_DVI_VSO_BEGIN_EVN 0x1c36 1039 #define ENCP_DVI_VSO_BEGIN_ODD 0x1c37 1040 #define ENCP_DVI_VSO_END_EVN 0x1c38 1041 #define ENCP_DVI_VSO_END_ODD 0x1c39 1042 #define ENCP_DE_H_BEGIN 0x1c3a 1043 #define ENCP_DE_H_END 0x1c3b 1044 #define ENCP_DE_V_BEGIN_EVEN 0x1c3c 1045 #define ENCP_DE_V_END_EVEN 0x1c3d 1046 #define ENCP_DE_V_BEGIN_ODD 0x1c3e 1047 #define ENCP_DE_V_END_ODD 0x1c3f 1048 #define ENCI_SYNC_LINE_LENGTH 0x1c40 1049 #define ENCI_SYNC_PIXEL_EN 0x1c41 1050 #define ENCI_SYNC_TO_LINE_EN 0x1c42 1051 #define ENCI_SYNC_TO_PIXEL 0x1c43 1052 #define ENCP_SYNC_LINE_LENGTH 0x1c44 1053 #define ENCP_SYNC_PIXEL_EN 0x1c45 1054 #define ENCP_SYNC_TO_LINE_EN 0x1c46 1055 #define ENCP_SYNC_TO_PIXEL 0x1c47 1056 #define ENCT_SYNC_LINE_LENGTH 0x1c48 1057 #define ENCT_SYNC_PIXEL_EN 0x1c49 1058 #define ENCT_SYNC_TO_LINE_EN 0x1c4a 1059 #define ENCT_SYNC_TO_PIXEL 0x1c4b 1060 #define ENCL_SYNC_LINE_LENGTH 0x1c4c 1061 #define ENCL_SYNC_PIXEL_EN 0x1c4d 1062 #define ENCL_SYNC_TO_LINE_EN 0x1c4e 1063 #define ENCL_SYNC_TO_PIXEL 0x1c4f 1064 #define ENCP_VFIFO2VD_CTL2 0x1c50 1065 #define VENC_DVI_SETTING_MORE 0x1c51 1066 #define VENC_VDAC_DAC4_FILT_CTRL0 0x1c54 1067 #define VENC_VDAC_DAC4_FILT_CTRL1 0x1c55 1068 #define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56 1069 #define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57 1070 #define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58 1071 #define VENC_VDAC_DAC0_FILT_CTRL0_EN BIT(0) 1072 #define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59 1073 #define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a 1074 #define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b 1075 #define VENC_VDAC_DAC2_FILT_CTRL0 0x1c5c 1076 #define VENC_VDAC_DAC2_FILT_CTRL1 0x1c5d 1077 #define VENC_VDAC_DAC3_FILT_CTRL0 0x1c5e 1078 #define VENC_VDAC_DAC3_FILT_CTRL1 0x1c5f 1079 #define ENCT_VIDEO_EN 0x1c60 1080 #define ENCT_VIDEO_Y_SCL 0x1c61 1081 #define ENCT_VIDEO_PB_SCL 0x1c62 1082 #define ENCT_VIDEO_PR_SCL 0x1c63 1083 #define ENCT_VIDEO_Y_OFFST 0x1c64 1084 #define ENCT_VIDEO_PB_OFFST 0x1c65 1085 #define ENCT_VIDEO_PR_OFFST 0x1c66 1086 #define ENCT_VIDEO_MODE 0x1c67 1087 #define ENCT_VIDEO_MODE_ADV 0x1c68 1088 #define ENCT_DBG_PX_RST 0x1c69 1089 #define ENCT_DBG_LN_RST 0x1c6a 1090 #define ENCT_DBG_PX_INT 0x1c6b 1091 #define ENCT_DBG_LN_INT 0x1c6c 1092 #define ENCT_VIDEO_YFP1_HTIME 0x1c6d 1093 #define ENCT_VIDEO_YFP2_HTIME 0x1c6e 1094 #define ENCT_VIDEO_YC_DLY 0x1c6f 1095 #define ENCT_VIDEO_MAX_PXCNT 0x1c70 1096 #define ENCT_VIDEO_HAVON_END 0x1c71 1097 #define ENCT_VIDEO_HAVON_BEGIN 0x1c72 1098 #define ENCT_VIDEO_VAVON_ELINE 0x1c73 1099 #define ENCT_VIDEO_VAVON_BLINE 0x1c74 1100 #define ENCT_VIDEO_HSO_BEGIN 0x1c75 1101 #define ENCT_VIDEO_HSO_END 0x1c76 1102 #define ENCT_VIDEO_VSO_BEGIN 0x1c77 1103 #define ENCT_VIDEO_VSO_END 0x1c78 1104 #define ENCT_VIDEO_VSO_BLINE 0x1c79 1105 #define ENCT_VIDEO_VSO_ELINE 0x1c7a 1106 #define ENCT_VIDEO_MAX_LNCNT 0x1c7b 1107 #define ENCT_VIDEO_BLANKY_VAL 0x1c7c 1108 #define ENCT_VIDEO_BLANKPB_VAL 0x1c7d 1109 #define ENCT_VIDEO_BLANKPR_VAL 0x1c7e 1110 #define ENCT_VIDEO_HOFFST 0x1c7f 1111 #define ENCT_VIDEO_VOFFST 0x1c80 1112 #define ENCT_VIDEO_RGB_CTRL 0x1c81 1113 #define ENCT_VIDEO_FILT_CTRL 0x1c82 1114 #define ENCT_VIDEO_OFLD_VPEQ_OFST 0x1c83 1115 #define ENCT_VIDEO_OFLD_VOAV_OFST 0x1c84 1116 #define ENCT_VIDEO_MATRIX_CB 0x1c85 1117 #define ENCT_VIDEO_MATRIX_CR 0x1c86 1118 #define ENCT_VIDEO_RGBIN_CTRL 0x1c87 1119 #define ENCT_MAX_LINE_SWITCH_POINT 0x1c88 1120 #define ENCT_DACSEL_0 0x1c89 1121 #define ENCT_DACSEL_1 0x1c8a 1122 #define ENCL_VFIFO2VD_CTL 0x1c90 1123 #define ENCL_VFIFO2VD_PIXEL_START 0x1c91 1124 #define ENCL_VFIFO2VD_PIXEL_END 0x1c92 1125 #define ENCL_VFIFO2VD_LINE_TOP_START 0x1c93 1126 #define ENCL_VFIFO2VD_LINE_TOP_END 0x1c94 1127 #define ENCL_VFIFO2VD_LINE_BOT_START 0x1c95 1128 #define ENCL_VFIFO2VD_LINE_BOT_END 0x1c96 1129 #define ENCL_VFIFO2VD_CTL2 0x1c97 1130 #define ENCL_TST_EN 0x1c98 1131 #define ENCL_TST_MDSEL 0x1c99 1132 #define ENCL_TST_Y 0x1c9a 1133 #define ENCL_TST_CB 0x1c9b 1134 #define ENCL_TST_CR 0x1c9c 1135 #define ENCL_TST_CLRBAR_STRT 0x1c9d 1136 #define ENCL_TST_CLRBAR_WIDTH 0x1c9e 1137 #define ENCL_TST_VDCNT_STSET 0x1c9f 1138 #define ENCL_VIDEO_EN 0x1ca0 1139 #define ENCL_VIDEO_Y_SCL 0x1ca1 1140 #define ENCL_VIDEO_PB_SCL 0x1ca2 1141 #define ENCL_VIDEO_PR_SCL 0x1ca3 1142 #define ENCL_VIDEO_Y_OFFST 0x1ca4 1143 #define ENCL_VIDEO_PB_OFFST 0x1ca5 1144 #define ENCL_VIDEO_PR_OFFST 0x1ca6 1145 #define ENCL_VIDEO_MODE 0x1ca7 1146 #define ENCL_VIDEO_MODE_ADV 0x1ca8 1147 #define ENCL_DBG_PX_RST 0x1ca9 1148 #define ENCL_DBG_LN_RST 0x1caa 1149 #define ENCL_DBG_PX_INT 0x1cab 1150 #define ENCL_DBG_LN_INT 0x1cac 1151 #define ENCL_VIDEO_YFP1_HTIME 0x1cad 1152 #define ENCL_VIDEO_YFP2_HTIME 0x1cae 1153 #define ENCL_VIDEO_YC_DLY 0x1caf 1154 #define ENCL_VIDEO_MAX_PXCNT 0x1cb0 1155 #define ENCL_VIDEO_HAVON_END 0x1cb1 1156 #define ENCL_VIDEO_HAVON_BEGIN 0x1cb2 1157 #define ENCL_VIDEO_VAVON_ELINE 0x1cb3 1158 #define ENCL_VIDEO_VAVON_BLINE 0x1cb4 1159 #define ENCL_VIDEO_HSO_BEGIN 0x1cb5 1160 #define ENCL_VIDEO_HSO_END 0x1cb6 1161 #define ENCL_VIDEO_VSO_BEGIN 0x1cb7 1162 #define ENCL_VIDEO_VSO_END 0x1cb8 1163 #define ENCL_VIDEO_VSO_BLINE 0x1cb9 1164 #define ENCL_VIDEO_VSO_ELINE 0x1cba 1165 #define ENCL_VIDEO_MAX_LNCNT 0x1cbb 1166 #define ENCL_VIDEO_BLANKY_VAL 0x1cbc 1167 #define ENCL_VIDEO_BLANKPB_VAL 0x1cbd 1168 #define ENCL_VIDEO_BLANKPR_VAL 0x1cbe 1169 #define ENCL_VIDEO_HOFFST 0x1cbf 1170 #define ENCL_VIDEO_VOFFST 0x1cc0 1171 #define ENCL_VIDEO_RGB_CTRL 0x1cc1 1172 #define ENCL_VIDEO_FILT_CTRL 0x1cc2 1173 #define ENCL_VIDEO_OFLD_VPEQ_OFST 0x1cc3 1174 #define ENCL_VIDEO_OFLD_VOAV_OFST 0x1cc4 1175 #define ENCL_VIDEO_MATRIX_CB 0x1cc5 1176 #define ENCL_VIDEO_MATRIX_CR 0x1cc6 1177 #define ENCL_VIDEO_RGBIN_CTRL 0x1cc7 1178 #define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8 1179 #define ENCL_DACSEL_0 0x1cc9 1180 #define ENCL_DACSEL_1 0x1cca 1181 #define RDMA_AHB_START_ADDR_MAN 0x1100 1182 #define RDMA_AHB_END_ADDR_MAN 0x1101 1183 #define RDMA_AHB_START_ADDR_1 0x1102 1184 #define RDMA_AHB_END_ADDR_1 0x1103 1185 #define RDMA_AHB_START_ADDR_2 0x1104 1186 #define RDMA_AHB_END_ADDR_2 0x1105 1187 #define RDMA_AHB_START_ADDR_3 0x1106 1188 #define RDMA_AHB_END_ADDR_3 0x1107 1189 #define RDMA_AHB_START_ADDR_4 0x1108 1190 #define RDMA_AHB_END_ADDR_4 0x1109 1191 #define RDMA_AHB_START_ADDR_5 0x110a 1192 #define RDMA_AHB_END_ADDR_5 0x110b 1193 #define RDMA_AHB_START_ADDR_6 0x110c 1194 #define RDMA_AHB_END_ADDR_6 0x110d 1195 #define RDMA_AHB_START_ADDR_7 0x110e 1196 #define RDMA_AHB_END_ADDR_7 0x110f 1197 #define RDMA_ACCESS_AUTO 0x1110 1198 #define RDMA_ACCESS_AUTO2 0x1111 1199 #define RDMA_ACCESS_AUTO3 0x1112 1200 #define RDMA_ACCESS_MAN 0x1113 1201 #define RDMA_CTRL 0x1114 1202 #define RDMA_STATUS 0x1115 1203 #define RDMA_STATUS2 0x1116 1204 #define RDMA_STATUS3 0x1117 1205 #define L_GAMMA_CNTL_PORT 0x1400 1206 #define L_GAMMA_DATA_PORT 0x1401 1207 #define L_GAMMA_ADDR_PORT 0x1402 1208 #define L_GAMMA_VCOM_HSWITCH_ADDR 0x1403 1209 #define L_RGB_BASE_ADDR 0x1405 1210 #define L_RGB_COEFF_ADDR 0x1406 1211 #define L_POL_CNTL_ADDR 0x1407 1212 #define L_DITH_CNTL_ADDR 0x1408 1213 #define L_GAMMA_PROBE_CTRL 0x1409 1214 #define L_GAMMA_PROBE_COLOR_L 0x140a 1215 #define L_GAMMA_PROBE_COLOR_H 0x140b 1216 #define L_GAMMA_PROBE_HL_COLOR 0x140c 1217 #define L_GAMMA_PROBE_POS_X 0x140d 1218 #define L_GAMMA_PROBE_POS_Y 0x140e 1219 #define L_STH1_HS_ADDR 0x1410 1220 #define L_STH1_HE_ADDR 0x1411 1221 #define L_STH1_VS_ADDR 0x1412 1222 #define L_STH1_VE_ADDR 0x1413 1223 #define L_STH2_HS_ADDR 0x1414 1224 #define L_STH2_HE_ADDR 0x1415 1225 #define L_STH2_VS_ADDR 0x1416 1226 #define L_STH2_VE_ADDR 0x1417 1227 #define L_OEH_HS_ADDR 0x1418 1228 #define L_OEH_HE_ADDR 0x1419 1229 #define L_OEH_VS_ADDR 0x141a 1230 #define L_OEH_VE_ADDR 0x141b 1231 #define L_VCOM_HSWITCH_ADDR 0x141c 1232 #define L_VCOM_VS_ADDR 0x141d 1233 #define L_VCOM_VE_ADDR 0x141e 1234 #define L_CPV1_HS_ADDR 0x141f 1235 #define L_CPV1_HE_ADDR 0x1420 1236 #define L_CPV1_VS_ADDR 0x1421 1237 #define L_CPV1_VE_ADDR 0x1422 1238 #define L_CPV2_HS_ADDR 0x1423 1239 #define L_CPV2_HE_ADDR 0x1424 1240 #define L_CPV2_VS_ADDR 0x1425 1241 #define L_CPV2_VE_ADDR 0x1426 1242 #define L_STV1_HS_ADDR 0x1427 1243 #define L_STV1_HE_ADDR 0x1428 1244 #define L_STV1_VS_ADDR 0x1429 1245 #define L_STV1_VE_ADDR 0x142a 1246 #define L_STV2_HS_ADDR 0x142b 1247 #define L_STV2_HE_ADDR 0x142c 1248 #define L_STV2_VS_ADDR 0x142d 1249 #define L_STV2_VE_ADDR 0x142e 1250 #define L_OEV1_HS_ADDR 0x142f 1251 #define L_OEV1_HE_ADDR 0x1430 1252 #define L_OEV1_VS_ADDR 0x1431 1253 #define L_OEV1_VE_ADDR 0x1432 1254 #define L_OEV2_HS_ADDR 0x1433 1255 #define L_OEV2_HE_ADDR 0x1434 1256 #define L_OEV2_VS_ADDR 0x1435 1257 #define L_OEV2_VE_ADDR 0x1436 1258 #define L_OEV3_HS_ADDR 0x1437 1259 #define L_OEV3_HE_ADDR 0x1438 1260 #define L_OEV3_VS_ADDR 0x1439 1261 #define L_OEV3_VE_ADDR 0x143a 1262 #define L_LCD_PWR_ADDR 0x143b 1263 #define L_LCD_PWM0_LO_ADDR 0x143c 1264 #define L_LCD_PWM0_HI_ADDR 0x143d 1265 #define L_LCD_PWM1_LO_ADDR 0x143e 1266 #define L_LCD_PWM1_HI_ADDR 0x143f 1267 #define L_INV_CNT_ADDR 0x1440 1268 #define L_TCON_MISC_SEL_ADDR 0x1441 1269 #define L_DUAL_PORT_CNTL_ADDR 0x1442 1270 #define MLVDS_CLK_CTL1_HI 0x1443 1271 #define MLVDS_CLK_CTL1_LO 0x1444 1272 #define L_TCON_DOUBLE_CTL 0x1449 1273 #define L_TCON_PATTERN_HI 0x144a 1274 #define L_TCON_PATTERN_LO 0x144b 1275 #define LDIM_BL_ADDR_PORT 0x144e 1276 #define LDIM_BL_DATA_PORT 0x144f 1277 #define L_DE_HS_ADDR 0x1451 1278 #define L_DE_HE_ADDR 0x1452 1279 #define L_DE_VS_ADDR 0x1453 1280 #define L_DE_VE_ADDR 0x1454 1281 #define L_HSYNC_HS_ADDR 0x1455 1282 #define L_HSYNC_HE_ADDR 0x1456 1283 #define L_HSYNC_VS_ADDR 0x1457 1284 #define L_HSYNC_VE_ADDR 0x1458 1285 #define L_VSYNC_HS_ADDR 0x1459 1286 #define L_VSYNC_HE_ADDR 0x145a 1287 #define L_VSYNC_VS_ADDR 0x145b 1288 #define L_VSYNC_VE_ADDR 0x145c 1289 #define L_LCD_MCU_CTL 0x145d 1290 #define DUAL_MLVDS_CTL 0x1460 1291 #define DUAL_MLVDS_LINE_START 0x1461 1292 #define DUAL_MLVDS_LINE_END 0x1462 1293 #define DUAL_MLVDS_PIXEL_W_START_L 0x1463 1294 #define DUAL_MLVDS_PIXEL_W_END_L 0x1464 1295 #define DUAL_MLVDS_PIXEL_W_START_R 0x1465 1296 #define DUAL_MLVDS_PIXEL_W_END_R 0x1466 1297 #define DUAL_MLVDS_PIXEL_R_START_L 0x1467 1298 #define DUAL_MLVDS_PIXEL_R_CNT_L 0x1468 1299 #define DUAL_MLVDS_PIXEL_R_START_R 0x1469 1300 #define DUAL_MLVDS_PIXEL_R_CNT_R 0x146a 1301 #define V_INVERSION_PIXEL 0x1470 1302 #define V_INVERSION_LINE 0x1471 1303 #define V_INVERSION_CONTROL 0x1472 1304 #define MLVDS2_CONTROL 0x1474 1305 #define MLVDS2_CONFIG_HI 0x1475 1306 #define MLVDS2_CONFIG_LO 0x1476 1307 #define MLVDS2_DUAL_GATE_WR_START 0x1477 1308 #define MLVDS2_DUAL_GATE_WR_END 0x1478 1309 #define MLVDS2_DUAL_GATE_RD_START 0x1479 1310 #define MLVDS2_DUAL_GATE_RD_END 0x147a 1311 #define MLVDS2_SECOND_RESET_CTL 0x147b 1312 #define MLVDS2_DUAL_GATE_CTL_HI 0x147c 1313 #define MLVDS2_DUAL_GATE_CTL_LO 0x147d 1314 #define MLVDS2_RESET_CONFIG_HI 0x147e 1315 #define MLVDS2_RESET_CONFIG_LO 0x147f 1316 #define GAMMA_CNTL_PORT 0x1480 1317 #define GAMMA_DATA_PORT 0x1481 1318 #define GAMMA_ADDR_PORT 0x1482 1319 #define GAMMA_VCOM_HSWITCH_ADDR 0x1483 1320 #define RGB_BASE_ADDR 0x1485 1321 #define RGB_COEFF_ADDR 0x1486 1322 #define POL_CNTL_ADDR 0x1487 1323 #define DITH_CNTL_ADDR 0x1488 1324 #define GAMMA_PROBE_CTRL 0x1489 1325 #define GAMMA_PROBE_COLOR_L 0x148a 1326 #define GAMMA_PROBE_COLOR_H 0x148b 1327 #define GAMMA_PROBE_HL_COLOR 0x148c 1328 #define GAMMA_PROBE_POS_X 0x148d 1329 #define GAMMA_PROBE_POS_Y 0x148e 1330 #define STH1_HS_ADDR 0x1490 1331 #define STH1_HE_ADDR 0x1491 1332 #define STH1_VS_ADDR 0x1492 1333 #define STH1_VE_ADDR 0x1493 1334 #define STH2_HS_ADDR 0x1494 1335 #define STH2_HE_ADDR 0x1495 1336 #define STH2_VS_ADDR 0x1496 1337 #define STH2_VE_ADDR 0x1497 1338 #define OEH_HS_ADDR 0x1498 1339 #define OEH_HE_ADDR 0x1499 1340 #define OEH_VS_ADDR 0x149a 1341 #define OEH_VE_ADDR 0x149b 1342 #define VCOM_HSWITCH_ADDR 0x149c 1343 #define VCOM_VS_ADDR 0x149d 1344 #define VCOM_VE_ADDR 0x149e 1345 #define CPV1_HS_ADDR 0x149f 1346 #define CPV1_HE_ADDR 0x14a0 1347 #define CPV1_VS_ADDR 0x14a1 1348 #define CPV1_VE_ADDR 0x14a2 1349 #define CPV2_HS_ADDR 0x14a3 1350 #define CPV2_HE_ADDR 0x14a4 1351 #define CPV2_VS_ADDR 0x14a5 1352 #define CPV2_VE_ADDR 0x14a6 1353 #define STV1_HS_ADDR 0x14a7 1354 #define STV1_HE_ADDR 0x14a8 1355 #define STV1_VS_ADDR 0x14a9 1356 #define STV1_VE_ADDR 0x14aa 1357 #define STV2_HS_ADDR 0x14ab 1358 #define STV2_HE_ADDR 0x14ac 1359 #define STV2_VS_ADDR 0x14ad 1360 #define STV2_VE_ADDR 0x14ae 1361 #define OEV1_HS_ADDR 0x14af 1362 #define OEV1_HE_ADDR 0x14b0 1363 #define OEV1_VS_ADDR 0x14b1 1364 #define OEV1_VE_ADDR 0x14b2 1365 #define OEV2_HS_ADDR 0x14b3 1366 #define OEV2_HE_ADDR 0x14b4 1367 #define OEV2_VS_ADDR 0x14b5 1368 #define OEV2_VE_ADDR 0x14b6 1369 #define OEV3_HS_ADDR 0x14b7 1370 #define OEV3_HE_ADDR 0x14b8 1371 #define OEV3_VS_ADDR 0x14b9 1372 #define OEV3_VE_ADDR 0x14ba 1373 #define LCD_PWR_ADDR 0x14bb 1374 #define LCD_PWM0_LO_ADDR 0x14bc 1375 #define LCD_PWM0_HI_ADDR 0x14bd 1376 #define LCD_PWM1_LO_ADDR 0x14be 1377 #define LCD_PWM1_HI_ADDR 0x14bf 1378 #define INV_CNT_ADDR 0x14c0 1379 #define TCON_MISC_SEL_ADDR 0x14c1 1380 #define DUAL_PORT_CNTL_ADDR 0x14c2 1381 #define MLVDS_CONTROL 0x14c3 1382 #define MLVDS_RESET_PATTERN_HI 0x14c4 1383 #define MLVDS_RESET_PATTERN_LO 0x14c5 1384 #define MLVDS_RESET_PATTERN_EXT 0x14c6 1385 #define MLVDS_CONFIG_HI 0x14c7 1386 #define MLVDS_CONFIG_LO 0x14c8 1387 #define TCON_DOUBLE_CTL 0x14c9 1388 #define TCON_PATTERN_HI 0x14ca 1389 #define TCON_PATTERN_LO 0x14cb 1390 #define TCON_CONTROL_HI 0x14cc 1391 #define TCON_CONTROL_LO 0x14cd 1392 #define LVDS_BLANK_DATA_HI 0x14ce 1393 #define LVDS_BLANK_DATA_LO 0x14cf 1394 #define LVDS_PACK_CNTL_ADDR 0x14d0 1395 #define DE_HS_ADDR 0x14d1 1396 #define DE_HE_ADDR 0x14d2 1397 #define DE_VS_ADDR 0x14d3 1398 #define DE_VE_ADDR 0x14d4 1399 #define HSYNC_HS_ADDR 0x14d5 1400 #define HSYNC_HE_ADDR 0x14d6 1401 #define HSYNC_VS_ADDR 0x14d7 1402 #define HSYNC_VE_ADDR 0x14d8 1403 #define VSYNC_HS_ADDR 0x14d9 1404 #define VSYNC_HE_ADDR 0x14da 1405 #define VSYNC_VS_ADDR 0x14db 1406 #define VSYNC_VE_ADDR 0x14dc 1407 #define LCD_MCU_CTL 0x14dd 1408 #define LCD_MCU_DATA_0 0x14de 1409 #define LCD_MCU_DATA_1 0x14df 1410 #define LVDS_GEN_CNTL 0x14e0 1411 #define LVDS_PHY_CNTL0 0x14e1 1412 #define LVDS_PHY_CNTL1 0x14e2 1413 #define LVDS_PHY_CNTL2 0x14e3 1414 #define LVDS_PHY_CNTL3 0x14e4 1415 #define LVDS_PHY_CNTL4 0x14e5 1416 #define LVDS_PHY_CNTL5 0x14e6 1417 #define LVDS_SRG_TEST 0x14e8 1418 #define LVDS_BIST_MUX0 0x14e9 1419 #define LVDS_BIST_MUX1 0x14ea 1420 #define LVDS_BIST_FIXED0 0x14eb 1421 #define LVDS_BIST_FIXED1 0x14ec 1422 #define LVDS_BIST_CNTL0 0x14ed 1423 #define LVDS_CLKB_CLKA 0x14ee 1424 #define LVDS_PHY_CLK_CNTL 0x14ef 1425 #define LVDS_SER_EN 0x14f0 1426 #define LVDS_PHY_CNTL6 0x14f1 1427 #define LVDS_PHY_CNTL7 0x14f2 1428 #define LVDS_PHY_CNTL8 0x14f3 1429 #define MLVDS_CLK_CTL0_HI 0x14f4 1430 #define MLVDS_CLK_CTL0_LO 0x14f5 1431 #define MLVDS_DUAL_GATE_WR_START 0x14f6 1432 #define MLVDS_DUAL_GATE_WR_END 0x14f7 1433 #define MLVDS_DUAL_GATE_RD_START 0x14f8 1434 #define MLVDS_DUAL_GATE_RD_END 0x14f9 1435 #define MLVDS_SECOND_RESET_CTL 0x14fa 1436 #define MLVDS_DUAL_GATE_CTL_HI 0x14fb 1437 #define MLVDS_DUAL_GATE_CTL_LO 0x14fc 1438 #define MLVDS_RESET_CONFIG_HI 0x14fd 1439 #define MLVDS_RESET_CONFIG_LO 0x14fe 1440 #define VPU_OSD1_MMC_CTRL 0x2701 1441 #define VPU_OSD2_MMC_CTRL 0x2702 1442 #define VPU_VD1_MMC_CTRL 0x2703 1443 #define VPU_VD2_MMC_CTRL 0x2704 1444 #define VPU_DI_IF1_MMC_CTRL 0x2705 1445 #define VPU_DI_MEM_MMC_CTRL 0x2706 1446 #define VPU_DI_INP_MMC_CTRL 0x2707 1447 #define VPU_DI_MTNRD_MMC_CTRL 0x2708 1448 #define VPU_DI_CHAN2_MMC_CTRL 0x2709 1449 #define VPU_DI_MTNWR_MMC_CTRL 0x270a 1450 #define VPU_DI_NRWR_MMC_CTRL 0x270b 1451 #define VPU_DI_DIWR_MMC_CTRL 0x270c 1452 #define VPU_VDIN0_MMC_CTRL 0x270d 1453 #define VPU_VDIN1_MMC_CTRL 0x270e 1454 #define VPU_BT656_MMC_CTRL 0x270f 1455 #define VPU_TVD3D_MMC_CTRL 0x2710 1456 #define VPU_TVDVBI_MMC_CTRL 0x2711 1457 #define VPU_TVDVBI_VSLATCH_ADDR 0x2712 1458 #define VPU_TVDVBI_WRRSP_ADDR 0x2713 1459 #define VPU_VDIN_PRE_ARB_CTRL 0x2714 1460 #define VPU_VDISP_PRE_ARB_CTRL 0x2715 1461 #define VPU_VPUARB2_PRE_ARB_CTRL 0x2716 1462 #define VPU_OSD3_MMC_CTRL 0x2717 1463 #define VPU_OSD4_MMC_CTRL 0x2718 1464 #define VPU_VD3_MMC_CTRL 0x2719 1465 #define VPU_VIU_VENC_MUX_CTRL 0x271a 1466 #define VIU1_SEL_VENC_MASK 0x3 1467 #define VIU1_SEL_VENC_ENCL 0 1468 #define VIU1_SEL_VENC_ENCI 1 1469 #define VIU1_SEL_VENC_ENCP 2 1470 #define VIU1_SEL_VENC_ENCT 3 1471 #define VIU2_SEL_VENC_MASK 0xc 1472 #define VIU2_SEL_VENC_ENCL 0 1473 #define VIU2_SEL_VENC_ENCI (1 << 2) 1474 #define VIU2_SEL_VENC_ENCP (2 << 2) 1475 #define VIU2_SEL_VENC_ENCT (3 << 2) 1476 #define VPU_HDMI_SETTING 0x271b 1477 #define VPU_HDMI_ENCI_DATA_TO_HDMI BIT(0) 1478 #define VPU_HDMI_ENCP_DATA_TO_HDMI BIT(1) 1479 #define VPU_HDMI_INV_HSYNC BIT(2) 1480 #define VPU_HDMI_INV_VSYNC BIT(3) 1481 #define VPU_HDMI_OUTPUT_CRYCB (0 << 5) 1482 #define VPU_HDMI_OUTPUT_YCBCR (1 << 5) 1483 #define VPU_HDMI_OUTPUT_YCRCB (2 << 5) 1484 #define VPU_HDMI_OUTPUT_CBCRY (3 << 5) 1485 #define VPU_HDMI_OUTPUT_CBYCR (4 << 5) 1486 #define VPU_HDMI_OUTPUT_CRCBY (5 << 5) 1487 #define VPU_HDMI_WR_RATE(rate) (((rate & 0x1f) - 1) << 8) 1488 #define VPU_HDMI_RD_RATE(rate) (((rate & 0x1f) - 1) << 12) 1489 #define ENCI_INFO_READ 0x271c 1490 #define ENCP_INFO_READ 0x271d 1491 #define ENCT_INFO_READ 0x271e 1492 #define ENCL_INFO_READ 0x271f 1493 #define VPU_SW_RESET 0x2720 1494 #define VPU_D2D3_MMC_CTRL 0x2721 1495 #define VPU_CONT_MMC_CTRL 0x2722 1496 #define VPU_CLK_GATE 0x2723 1497 #define VPU_RDMA_MMC_CTRL 0x2724 1498 #define VPU_MEM_PD_REG0 0x2725 1499 #define VPU_MEM_PD_REG1 0x2726 1500 #define VPU_HDMI_DATA_OVR 0x2727 1501 #define VPU_PROT1_MMC_CTRL 0x2728 1502 #define VPU_PROT2_MMC_CTRL 0x2729 1503 #define VPU_PROT3_MMC_CTRL 0x272a 1504 #define VPU_ARB4_V1_MMC_CTRL 0x272b 1505 #define VPU_ARB4_V2_MMC_CTRL 0x272c 1506 #define VPU_VPU_PWM_V0 0x2730 1507 #define VPU_VPU_PWM_V1 0x2731 1508 #define VPU_VPU_PWM_V2 0x2732 1509 #define VPU_VPU_PWM_V3 0x2733 1510 #define VPU_VPU_PWM_H0 0x2734 1511 #define VPU_VPU_PWM_H1 0x2735 1512 #define VPU_VPU_PWM_H2 0x2736 1513 #define VPU_VPU_PWM_H3 0x2737 1514 #define VPU_MISC_CTRL 0x2740 1515 #define VPU_ISP_GCLK_CTRL0 0x2741 1516 #define VPU_ISP_GCLK_CTRL1 0x2742 1517 #define VPU_HDMI_FMT_CTRL 0x2743 1518 #define VPU_VDIN_ASYNC_HOLD_CTRL 0x2743 1519 #define VPU_VDISP_ASYNC_HOLD_CTRL 0x2744 1520 #define VPU_VPUARB2_ASYNC_HOLD_CTRL 0x2745 1521 1522 #define VPU_PROT1_CLK_GATE 0x2750 1523 #define VPU_PROT1_GEN_CNTL 0x2751 1524 #define VPU_PROT1_X_START_END 0x2752 1525 #define VPU_PROT1_Y_START_END 0x2753 1526 #define VPU_PROT1_Y_LEN_STEP 0x2754 1527 #define VPU_PROT1_RPT_LOOP 0x2755 1528 #define VPU_PROT1_RPT_PAT 0x2756 1529 #define VPU_PROT1_DDR 0x2757 1530 #define VPU_PROT1_RBUF_ROOM 0x2758 1531 #define VPU_PROT1_STAT_0 0x2759 1532 #define VPU_PROT1_STAT_1 0x275a 1533 #define VPU_PROT1_STAT_2 0x275b 1534 #define VPU_PROT1_REQ_ONOFF 0x275c 1535 #define VPU_PROT2_CLK_GATE 0x2760 1536 #define VPU_PROT2_GEN_CNTL 0x2761 1537 #define VPU_PROT2_X_START_END 0x2762 1538 #define VPU_PROT2_Y_START_END 0x2763 1539 #define VPU_PROT2_Y_LEN_STEP 0x2764 1540 #define VPU_PROT2_RPT_LOOP 0x2765 1541 #define VPU_PROT2_RPT_PAT 0x2766 1542 #define VPU_PROT2_DDR 0x2767 1543 #define VPU_PROT2_RBUF_ROOM 0x2768 1544 #define VPU_PROT2_STAT_0 0x2769 1545 #define VPU_PROT2_STAT_1 0x276a 1546 #define VPU_PROT2_STAT_2 0x276b 1547 #define VPU_PROT2_REQ_ONOFF 0x276c 1548 #define VPU_PROT3_CLK_GATE 0x2770 1549 #define VPU_PROT3_GEN_CNTL 0x2771 1550 #define VPU_PROT3_X_START_END 0x2772 1551 #define VPU_PROT3_Y_START_END 0x2773 1552 #define VPU_PROT3_Y_LEN_STEP 0x2774 1553 #define VPU_PROT3_RPT_LOOP 0x2775 1554 #define VPU_PROT3_RPT_PAT 0x2776 1555 #define VPU_PROT3_DDR 0x2777 1556 #define VPU_PROT3_RBUF_ROOM 0x2778 1557 #define VPU_PROT3_STAT_0 0x2779 1558 #define VPU_PROT3_STAT_1 0x277a 1559 #define VPU_PROT3_STAT_2 0x277b 1560 #define VPU_PROT3_REQ_ONOFF 0x277c 1561 #define VPU_RDARB_MODE_L1C1 0x2790 1562 #define VPU_RDARB_MODE_L1C2 0x2799 1563 #define VPU_RDARB_MODE_L2C1 0x279d 1564 #define VPU_WRARB_MODE_L2C1 0x27a2 1565 #define VPU_RDARB_SLAVE_TO_MASTER_PORT(dc, port) (port << (16 + dc)) 1566 1567 /* osd super scale */ 1568 #define OSDSR_HV_SIZEIN 0x3130 1569 #define OSDSR_CTRL_MODE 0x3131 1570 #define OSDSR_ABIC_HCOEF 0x3132 1571 #define OSDSR_YBIC_HCOEF 0x3133 1572 #define OSDSR_CBIC_HCOEF 0x3134 1573 #define OSDSR_ABIC_VCOEF 0x3135 1574 #define OSDSR_YBIC_VCOEF 0x3136 1575 #define OSDSR_CBIC_VCOEF 0x3137 1576 #define OSDSR_VAR_PARA 0x3138 1577 #define OSDSR_CONST_PARA 0x3139 1578 #define OSDSR_RKE_EXTWIN 0x313a 1579 #define OSDSR_UK_GRAD2DDIAG_TH_RATE 0x313b 1580 #define OSDSR_UK_GRAD2DDIAG_LIMIT 0x313c 1581 #define OSDSR_UK_GRAD2DADJA_TH_RATE 0x313d 1582 #define OSDSR_UK_GRAD2DADJA_LIMIT 0x313e 1583 #define OSDSR_UK_BST_GAIN 0x313f 1584 #define OSDSR_HVBLEND_TH 0x3140 1585 #define OSDSR_DEMO_WIND_TB 0x3141 1586 #define OSDSR_DEMO_WIND_LR 0x3142 1587 #define OSDSR_INT_BLANK_NUM 0x3143 1588 #define OSDSR_FRM_END_STAT 0x3144 1589 #define OSDSR_ABIC_HCOEF0 0x3145 1590 #define OSDSR_YBIC_HCOEF0 0x3146 1591 #define OSDSR_CBIC_HCOEF0 0x3147 1592 #define OSDSR_ABIC_VCOEF0 0x3148 1593 #define OSDSR_YBIC_VCOEF0 0x3149 1594 #define OSDSR_CBIC_VCOEF0 0x314a 1595 1596 /* osd afbcd on gxtvbb */ 1597 #define OSD1_AFBCD_ENABLE 0x31a0 1598 #define OSD1_AFBCD_MODE 0x31a1 1599 #define OSD1_AFBCD_SIZE_IN 0x31a2 1600 #define OSD1_AFBCD_HDR_PTR 0x31a3 1601 #define OSD1_AFBCD_FRAME_PTR 0x31a4 1602 #define OSD1_AFBCD_CHROMA_PTR 0x31a5 1603 #define OSD1_AFBCD_CONV_CTRL 0x31a6 1604 #define OSD1_AFBCD_STATUS 0x31a8 1605 #define OSD1_AFBCD_PIXEL_HSCOPE 0x31a9 1606 #define OSD1_AFBCD_PIXEL_VSCOPE 0x31aa 1607 1608 /* add for gxm and 962e dv core2 */ 1609 #define DOLBY_CORE2A_SWAP_CTRL1 0x3434 1610 #define DOLBY_CORE2A_SWAP_CTRL2 0x3435 1611 1612 /* osd afbc on g12a */ 1613 #define VPU_MAFBC_BLOCK_ID 0x3a00 1614 #define VPU_MAFBC_IRQ_RAW_STATUS 0x3a01 1615 #define VPU_MAFBC_IRQ_CLEAR 0x3a02 1616 #define VPU_MAFBC_IRQ_MASK 0x3a03 1617 #define VPU_MAFBC_IRQ_STATUS 0x3a04 1618 #define VPU_MAFBC_COMMAND 0x3a05 1619 #define VPU_MAFBC_STATUS 0x3a06 1620 #define VPU_MAFBC_SURFACE_CFG 0x3a07 1621 #define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 0x3a10 1622 #define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 0x3a11 1623 #define VPU_MAFBC_FORMAT_SPECIFIER_S0 0x3a12 1624 #define VPU_MAFBC_BUFFER_WIDTH_S0 0x3a13 1625 #define VPU_MAFBC_BUFFER_HEIGHT_S0 0x3a14 1626 #define VPU_MAFBC_BOUNDING_BOX_X_START_S0 0x3a15 1627 #define VPU_MAFBC_BOUNDING_BOX_X_END_S0 0x3a16 1628 #define VPU_MAFBC_BOUNDING_BOX_Y_START_S0 0x3a17 1629 #define VPU_MAFBC_BOUNDING_BOX_Y_END_S0 0x3a18 1630 #define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0 0x3a19 1631 #define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0 0x3a1a 1632 #define VPU_MAFBC_OUTPUT_BUF_STRIDE_S0 0x3a1b 1633 #define VPU_MAFBC_PREFETCH_CFG_S0 0x3a1c 1634 1635 #define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1 0x3a30 1636 #define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1 0x3a31 1637 #define VPU_MAFBC_FORMAT_SPECIFIER_S1 0x3a32 1638 #define VPU_MAFBC_BUFFER_WIDTH_S1 0x3a33 1639 #define VPU_MAFBC_BUFFER_HEIGHT_S1 0x3a34 1640 #define VPU_MAFBC_BOUNDING_BOX_X_START_S1 0x3a35 1641 #define VPU_MAFBC_BOUNDING_BOX_X_END_S1 0x3a36 1642 #define VPU_MAFBC_BOUNDING_BOX_Y_START_S1 0x3a37 1643 #define VPU_MAFBC_BOUNDING_BOX_Y_END_S1 0x3a38 1644 #define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S1 0x3a39 1645 #define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S1 0x3a3a 1646 #define VPU_MAFBC_OUTPUT_BUF_STRIDE_S1 0x3a3b 1647 #define VPU_MAFBC_PREFETCH_CFG_S1 0x3a3c 1648 1649 #define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2 0x3a50 1650 #define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S2 0x3a51 1651 #define VPU_MAFBC_FORMAT_SPECIFIER_S2 0x3a52 1652 #define VPU_MAFBC_BUFFER_WIDTH_S2 0x3a53 1653 #define VPU_MAFBC_BUFFER_HEIGHT_S2 0x3a54 1654 #define VPU_MAFBC_BOUNDING_BOX_X_START_S2 0x3a55 1655 #define VPU_MAFBC_BOUNDING_BOX_X_END_S2 0x3a56 1656 #define VPU_MAFBC_BOUNDING_BOX_Y_START_S2 0x3a57 1657 #define VPU_MAFBC_BOUNDING_BOX_Y_END_S2 0x3a58 1658 #define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S2 0x3a59 1659 #define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S2 0x3a5a 1660 #define VPU_MAFBC_OUTPUT_BUF_STRIDE_S2 0x3a5b 1661 #define VPU_MAFBC_PREFETCH_CFG_S2 0x3a5c 1662 1663 #define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S3 0x3a70 1664 #define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S3 0x3a71 1665 #define VPU_MAFBC_FORMAT_SPECIFIER_S3 0x3a72 1666 #define VPU_MAFBC_BUFFER_WIDTH_S3 0x3a73 1667 #define VPU_MAFBC_BUFFER_HEIGHT_S3 0x3a74 1668 #define VPU_MAFBC_BOUNDING_BOX_X_START_S3 0x3a75 1669 #define VPU_MAFBC_BOUNDING_BOX_X_END_S3 0x3a76 1670 #define VPU_MAFBC_BOUNDING_BOX_Y_START_S3 0x3a77 1671 #define VPU_MAFBC_BOUNDING_BOX_Y_END_S3 0x3a78 1672 #define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S3 0x3a79 1673 #define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S3 0x3a7a 1674 #define VPU_MAFBC_OUTPUT_BUF_STRIDE_S3 0x3a7b 1675 #define VPU_MAFBC_PREFETCH_CFG_S3 0x3a7c 1676 1677 #define DOLBY_PATH_CTRL 0x1a0c 1678 #define DOLBY_BYPASS_EN(val) (val & 0xf) 1679 #define OSD_PATH_MISC_CTRL 0x1a0e 1680 #define MALI_AFBCD_TOP_CTRL 0x1a0f 1681 1682 #define VIU_OSD_BLEND_CTRL 0x39b0 1683 #define VIU_OSD_BLEND_REORDER(dest, src) ((src) << (dest * 4)) 1684 #define VIU_OSD_BLEND_DIN_EN(bits) ((bits & 0xf) << 20) 1685 #define VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 BIT(24) 1686 #define VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 BIT(25) 1687 #define VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 BIT(26) 1688 #define VIU_OSD_BLEND_BLEN2_PREMULT_EN(input) ((input & 0x3) << 27) 1689 #define VIU_OSD_BLEND_HOLD_LINES(lines) ((lines & 0x7) << 29) 1690 #define VIU_OSD_BLEND_CTRL1 0x39c0 1691 #define VIU_OSD_BLEND_DIN0_SCOPE_H 0x39b1 1692 #define VIU_OSD_BLEND_DIN0_SCOPE_V 0x39b2 1693 #define VIU_OSD_BLEND_DIN1_SCOPE_H 0x39b3 1694 #define VIU_OSD_BLEND_DIN1_SCOPE_V 0x39b4 1695 #define VIU_OSD_BLEND_DIN2_SCOPE_H 0x39b5 1696 #define VIU_OSD_BLEND_DIN2_SCOPE_V 0x39b6 1697 #define VIU_OSD_BLEND_DIN3_SCOPE_H 0x39b7 1698 #define VIU_OSD_BLEND_DIN3_SCOPE_V 0x39b8 1699 #define VIU_OSD_BLEND_DUMMY_DATA0 0x39b9 1700 #define VIU_OSD_BLEND_DUMMY_ALPHA 0x39ba 1701 #define VIU_OSD_BLEND_BLEND0_SIZE 0x39bb 1702 #define VIU_OSD_BLEND_BLEND1_SIZE 0x39bc 1703 #define VIU_OSD_BLEND_RO_CURRENT_XY 0x39bf 1704 1705 #define VPP_OUT_H_V_SIZE 0x1da5 1706 1707 #define VPP_VD2_HDR_IN_SIZE 0x1df0 1708 #define VPP_OSD1_IN_SIZE 0x1df1 1709 #define VPP_GCLK_CTRL2 0x1df2 1710 #define VD2_PPS_DUMMY_DATA 0x1df4 1711 #define VPP_OSD1_BLD_H_SCOPE 0x1df5 1712 #define VPP_OSD1_BLD_V_SCOPE 0x1df6 1713 #define VPP_OSD2_BLD_H_SCOPE 0x1df7 1714 #define VPP_OSD2_BLD_V_SCOPE 0x1df8 1715 #define VPP_WRBAK_CTRL 0x1df9 1716 #define VPP_SLEEP_CTRL 0x1dfa 1717 #define VD1_BLEND_SRC_CTRL 0x1dfb 1718 #define VD2_BLEND_SRC_CTRL 0x1dfc 1719 #define VD_BLEND_PREBLD_SRC_VD1 (1 << 0) 1720 #define VD_BLEND_PREBLD_SRC_VD2 (2 << 0) 1721 #define VD_BLEND_PREBLD_SRC_OSD1 (3 << 0) 1722 #define VD_BLEND_PREBLD_SRC_OSD2 (4 << 0) 1723 #define VD_BLEND_PREBLD_PREMULT_EN BIT(4) 1724 #define VD_BLEND_POSTBLD_SRC_VD1 (1 << 8) 1725 #define VD_BLEND_POSTBLD_SRC_VD2 (2 << 8) 1726 #define VD_BLEND_POSTBLD_SRC_OSD1 (3 << 8) 1727 #define VD_BLEND_POSTBLD_SRC_OSD2 (4 << 8) 1728 #define VD_BLEND_POSTBLD_PREMULT_EN BIT(16) 1729 #define OSD1_BLEND_SRC_CTRL 0x1dfd 1730 #define OSD2_BLEND_SRC_CTRL 0x1dfe 1731 #define OSD_BLEND_POSTBLD_SRC_VD1 (1 << 8) 1732 #define OSD_BLEND_POSTBLD_SRC_VD2 (2 << 8) 1733 #define OSD_BLEND_POSTBLD_SRC_OSD1 (3 << 8) 1734 #define OSD_BLEND_POSTBLD_SRC_OSD2 (4 << 8) 1735 #define OSD_BLEND_PATH_SEL_ENABLE BIT(20) 1736 1737 #define VPP_POST_BLEND_BLEND_DUMMY_DATA 0x3968 1738 #define VPP_POST_BLEND_DUMMY_ALPHA 0x3969 1739 #define VPP_RDARB_MODE 0x3978 1740 #define VPP_RDARB_REQEN_SLV 0x3979 1741 1742 #endif /* __MESON_REGISTERS_H */ 1743
