| /Linux-v5.4/Documentation/devicetree/bindings/memory-controllers/ |
| D | synopsys.txt | 3 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
6 The Zynq DDR ECC controller has an optional ECC support in half-bus width
14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
16 - reg: Should contain DDR controller registers location and length.
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| D | calxeda-ddr-ctrlr.txt | 1 Calxeda DDR memory controller
7 - reg : Address and size for DDR controller registers.
8 - interrupts : Interrupt for DDR controller.
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| D | ath79-ddr-controller.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
3 The DDR controller of the AR7xxx and AR9xxx families provides an interface
4 to flush the FIFO between various devices and the DDR. This is mainly used
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| D | brcm,dpfe-cpu.txt | 1 DDR PHY Front End (DPFE) for Broadcom STB
5 communicate with the DCPU, which resides inside the DDR PHY.
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| /Linux-v5.4/Documentation/devicetree/bindings/mips/brcm/ |
| D | soc.txt | 45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
95 - reg : the DDR PHY register range and length
104 == DDR memory controller sequencer
106 Control registers for this memory controller's DDR memory sequencer
115 - reg : the DDR sequencer register range and length
136 - reg : the DDR Arbiter register range and length
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| /Linux-v5.4/Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | ddr.txt | 1 Freescale DDR memory controller
8 - reg : Address and size of DDR controller registers
9 - interrupts : Error interrupt of DDR controller
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| D | mmdc.txt | 1 Freescale Multi Mode DDR controller (MMDC)
19 - reg : address and size of MMDC DDR controller registers
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| /Linux-v5.4/Documentation/ABI/testing/ |
| D | sysfs-driver-bd9571mwv-regulator | 5 Description: Read/write the current state of DDR Backup Mode, which controls
6 if DDR power rails will be kept powered during system suspend.
9 A. With a momentary power switch (or pulse signal), DDR
23 DDR Backup Mode must be explicitly enabled by the user,
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| /Linux-v5.4/Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 12 4 = dramclk (DDR clock)
18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
37 2 = ddrclk (DDR clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
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| D | brcm,bcm2835-cprman.txt | 27 - DSI0 DDR clock
30 - DSI1 DDR clock
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| D | armada3700-periph-clock.txt | 26 11 ddr_phy DDR PHY
27 12 ddr_fclk DDR F clock
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| /Linux-v5.4/Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,brcmstb.txt | 148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
179 Control registers for this memory controller's DDR SHIMPHY.
183 - reg : the DDR SHIMPHY register range
185 == MEMC DDR control
198 - reg : the MEMC DDR register range
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| /Linux-v5.4/drivers/gpio/ |
| D | gpio-mb86s7x.c | 31 #define DDR(x) (0x10 + x / 8 * 4) macro
83 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
85 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
108 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
110 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
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| /Linux-v5.4/drivers/memory/ |
| D | Kconfig | 11 config DDR config
14 Data from JEDEC specs for DDR SDRAM memories,
17 DDR SDRAM controllers.
28 bool "Atmel (Multi-port DDR-)SDRAM Controller"
33 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
34 Starting with the at91sam9g45, this controller supports SDR, DDR and
35 LP-DDR memories.
63 select DDR
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| /Linux-v5.4/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 5 - devfreq-events: Node to get DDR loading, Refer to
19 It should be a DCF interrupt. When DDR DVFS finishes
22 Following properties relate to DDR timing:
61 When DDR frequency is less than DRAM_DLL_DISB_FREQ,
66 MHz (Mega Hz). When DDR frequency is less than
72 when the DDR frequency is less then ddr3_odt_dis_freq,
99 When DDR frequency is less then ddr3_odt_dis_freq,
127 MHz (Mega Hz). When the DDR frequency is less then
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| /Linux-v5.4/drivers/mtd/lpddr/ |
| D | Kconfig | 10 flash chips. Synonymous with Mobile-DDR. It is a new standard for
11 DDR memories, intended for battery-operated systems.
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| /Linux-v5.4/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 55 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
75 movs r0, r0 @ see if DDR or SDR
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| /Linux-v5.4/Documentation/devicetree/bindings/lpddr2/ |
| D | lpddr2-timings.txt | 5 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6 - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
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| /Linux-v5.4/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx7ulp-pinctrl.txt | 4 ports and IOMUXC DDR for DDR interface.
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| /Linux-v5.4/Documentation/driver-api/memory-devices/ |
| D | ti-emif.rst | 38 DDR device details and other board dependent and SoC dependent
41 - DDR device details: 'struct ddr_device_info'
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| /Linux-v5.4/Documentation/devicetree/bindings/mips/img/ |
| D | xilfpga.txt | 20 - 128Mbyte DDR RAM at 0x0000_0000
74 DDR initialization is already handled by a HW IP block.
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| /Linux-v5.4/Documentation/devicetree/bindings/mfd/ |
| D | bd9571mwv.txt | 28 - rohm,ddr-backup-power : Value to use for DDR-Backup Power (default 0).
29 This is a bitmask that specifies which DDR power
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| /Linux-v5.4/Documentation/arm/samsung-s3c24xx/ |
| D | s3c2413.rst | 9 interface and mobile DDR memory support. See the S3C2412 support
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| /Linux-v5.4/Documentation/devicetree/bindings/perf/ |
| D | fsl-imx-ddr.txt | 1 * Freescale(NXP) IMX8 DDR performance monitor
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| /Linux-v5.4/Documentation/devicetree/bindings/reset/ |
| D | amlogic,meson-axg-audio-arb.txt | 4 disables the access of Audio FIFOs to DDR on AXG based SoC.
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