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Searched refs:DCACHE_WAY_SIZE (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.4/arch/xtensa/include/asm/
Dcache.h20 #define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) macro
26 #if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE
27 # define CACHE_WAY_SIZE DCACHE_WAY_SIZE
Dshmparam.h19 #define SHMLBA ((PAGE_SIZE > DCACHE_WAY_SIZE)? PAGE_SIZE : DCACHE_WAY_SIZE)
Dcacheflush.h69 #if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
95 ((DCACHE_WAY_SIZE > PAGE_SIZE) || defined(CONFIG_SMP))
161 #if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
Dpage.h66 #if DCACHE_WAY_SIZE > PAGE_SIZE
68 # define DCACHE_ALIAS_MASK (PAGE_MASK & (DCACHE_WAY_SIZE - 1))
140 #if defined(CONFIG_MMU) && DCACHE_WAY_SIZE > PAGE_SIZE
Dpgtable.h74 #define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
75 #if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
76 #define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE)
181 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
313 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK in update_pte()
Dhighmem.h30 #if DCACHE_WAY_SIZE > PAGE_SIZE
/Linux-v5.4/Documentation/xtensa/
Dmmu.rst85 | Cache aliasing | TLBTEMP_BASE_1 0xc7ff0000 DCACHE_WAY_SIZE
88 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
127 | Cache aliasing | TLBTEMP_BASE_1 0xa7ff0000 DCACHE_WAY_SIZE
130 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
170 | Cache aliasing | TLBTEMP_BASE_1 0x97ff0000 DCACHE_WAY_SIZE
173 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
/Linux-v5.4/arch/xtensa/mm/
Dcache.c59 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
225 #if (DCACHE_WAY_SIZE > PAGE_SIZE) in update_mmu_cache()
256 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
Dhighmem.c17 #if DCACHE_WAY_SIZE > PAGE_SIZE
Dmisc.S110 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
242 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
/Linux-v5.4/arch/xtensa/kernel/
Dentry.S1690 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
1821 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK