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Searched refs:CTR (Results 1 – 17 of 17) sorted by relevance

/Linux-v5.4/arch/x86/crypto/
Daesni-intel_avx-x86_64.S1003 .macro INITIAL_BLOCKS_AVX REP num_initial_blocks T1 T2 T3 T4 T5 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 X…
1009 vmovdqu CurCount(arg2), \CTR
1014 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1015 vmovdqa \CTR, reg_i
1092 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1093 vmovdqa \CTR, \XMM1
1096 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1097 vmovdqa \CTR, \XMM2
1100 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1101 vmovdqa \CTR, \XMM3
[all …]
Daesni-intel_asm.S147 #define CTR %xmm11 macro
2610 movaps IV, CTR
2611 PSHUFB_XMM BSWAP_MASK CTR
2614 MOVQ_R64_XMM CTR TCTR_LOW
2635 paddq INC, CTR
2639 paddq INC, CTR
2642 movaps CTR, IV
2722 pshufd $0x13, IV, CTR; \
2724 psrad $31, CTR; \
2725 pand GF128MUL_MASK, CTR; \
[all …]
/Linux-v5.4/tools/perf/arch/powerpc/tests/
Dregs_load.S38 #define CTR 35 * 8 macro
90 std 4, CTR(3)
/Linux-v5.4/arch/arm64/crypto/
DKconfig87 tristate "AES in ECB/CBC/CTR/XTS modes using ARMv8 Crypto Extensions"
95 tristate "AES in ECB/CBC/CTR/XTS modes using NEON instructions"
114 tristate "AES in ECB/CBC/CTR/XTS modes using bit-sliced NEON algorithm"
/Linux-v5.4/Documentation/crypto/
Darchitecture.rst269 the AES-NI implementation, the CTR mode, the GHASH implementation and
336 During instantiation of the GCM handle, the CTR(AES) and GHASH
337 ciphers are instantiated. The cipher handles for CTR(AES) and GHASH
340 The GCM implementation is responsible to invoke the CTR mode AES and
345 with the instantiated CTR(AES) cipher handle.
347 During instantiation of the CTR(AES) cipher, the CIPHER type
351 That means that the SKCIPHER implementation of CTR(AES) only
352 implements the CTR block chaining mode. After performing the block
355 4. The SKCIPHER of CTR(AES) now invokes the CIPHER API with the AES
/Linux-v5.4/arch/arm/crypto/
DKconfig89 CTR and XTS modes
91 Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
104 Use an implementation of AES in CBC, CTR and XTS modes that uses
Daes-ce-core.S437 vst1.8 {q7}, [r5] @ return next CTR value
/Linux-v5.4/Documentation/devicetree/bindings/crypto/
Dsamsung-slimsss.txt5 -- Advanced Encryption Standard (AES) with ECB,CBC,CTR,XTS and (CBC/XTS)/CTS
/Linux-v5.4/drivers/spi/
Dspi-sh-msiof.c74 #define CTR 0x28 /* Control Register */ macro
226 data = sh_msiof_read(p, CTR); in sh_msiof_modify_ctr_wait()
229 sh_msiof_write(p, CTR, data); in sh_msiof_modify_ctr_wait()
231 return readl_poll_timeout_atomic(p->mapbase + CTR, data, in sh_msiof_modify_ctr_wait()
251 data = sh_msiof_read(p, CTR); in sh_msiof_spi_reset_regs()
253 sh_msiof_write(p, CTR, data); in sh_msiof_spi_reset_regs()
255 readl_poll_timeout_atomic(p->mapbase + CTR, data, !(data & mask), 1, in sh_msiof_spi_reset_regs()
386 sh_msiof_write(p, CTR, tmp); in sh_msiof_spi_set_pin_regs()
/Linux-v5.4/drivers/crypto/ux500/
DKconfig15 AES-ECB, CBC and CTR with keys sizes of 128, 192 and 256 bit sizes.
/Linux-v5.4/drivers/platform/x86/
Dintel_telemetry_debugfs.c76 #define TELEM_CHECK_AND_PARSE_CTRS(EVTID, CTR) { \ argument
78 (CTR) = evtlog[index].telem_evtlog; \
Dsony-laptop.c711 SNC_HANDLE(CTR, snc_CTR_get, snc_CTR_set, NULL, 1),
/Linux-v5.4/arch/powerpc/platforms/8xx/
DKconfig129 (by not placing conditional branches or branches to LR or CTR
/Linux-v5.4/crypto/
DKconfig331 xoring it with a salt. This algorithm is mainly useful for CTR
363 tristate "CTR support"
368 CTR: Counter mode
1053 and GCM drivers, and other CTR or CMAC/XCBC based modes that rely
1095 acceleration for CTR.
1130 for popular block cipher modes ECB, CBC, CTR and XTS is supported.
1767 bool "Enable CTR DRBG"
1771 Enable the CTR DRBG variant as defined in NIST SP800-90A.
/Linux-v5.4/Documentation/powerpc/
Dtransactional_memory.rst63 Checkpointed registers include all GPRs, FPRs, VRs/VSRs, LR, CCR/CR, CTR, FPCSR
/Linux-v5.4/drivers/crypto/
DKconfig179 As of z196 the CTR mode is hardware accelerated.
194 As of z196 the CTR mode is hardware accelerated for all AES
/Linux-v5.4/arch/arm/kvm/
Dcoproc.c814 FUNCTION_FOR32(0, 0, 0, 1, CTR)