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Searched refs:CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2119 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_gfx_resume()
Dgfx_v7_0.c2630 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v7_0_cp_gfx_resume()
Dgfx_v8_0.c4317 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v8_0_cp_gfx_resume()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h2724 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L macro
Dgfx_7_2_sh_mask.h1057 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
Dgfx_8_1_sh_mask.h1897 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
Dgfx_8_0_sh_mask.h1373 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h10683 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_9_2_1_sh_mask.h11991 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_9_1_sh_mask.h12186 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_10_1_0_sh_mask.h17612 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK … macro