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Searched refs:CP_MEC_CNTL__MEC_ME2_HALT_MASK (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c2708 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v7_0_cp_compute_enable()
4667 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); in gfx_v7_0_soft_reset()
Dgfx_v10_0.c2885 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v10_0_cp_compute_enable()
Dgfx_v9_0.c3279 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v9_0_cp_compute_enable()
Dgfx_v8_0.c4352 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v8_0_cp_compute_enable()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h2221 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 macro
Dgfx_8_1_sh_mask.h3289 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 macro
Dgfx_8_0_sh_mask.h2767 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h846 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro
Dgc_9_2_1_sh_mask.h734 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro
Dgc_9_1_sh_mask.h745 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro
Dgc_10_1_0_sh_mask.h6321 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro