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Searched refs:CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h1429 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 macro
Dgfx_8_1_sh_mask.h2337 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 macro
Dgfx_8_0_sh_mask.h1813 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h11159 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK … macro
Dgc_9_1_sh_mask.h12662 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK … macro
Dgc_10_1_0_sh_mask.h18136 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK … macro