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Searched refs:CP_ME1_PIPE0_INT_CNTL (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/radeon/
Dcikd.h1358 #define CP_ME1_PIPE0_INT_CNTL 0xC214 macro
Dcik.c6883 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
7066 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7237 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); in cik_irq_set()
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c4893 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
4899 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
Dgfx_v9_0.c5537 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
5543 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
Dgfx_v8_0.c6665 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()