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Searched refs:CPG_PLL0CR (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/clk/renesas/
Dclk-r8a73a4.c28 #define CPG_PLL0CR 0xd8 macro
96 u32 value = readl(cpg->reg + CPG_PLL0CR); in r8a73a4_cpg_register_clock()
Dclk-sh73a0.c30 #define CPG_PLL0CR 0xd8 macro
97 enable_reg += CPG_PLL0CR; in sh73a0_cpg_register_clock()
Drcar-gen2-cpg.c24 #define CPG_PLL0CR 0x00d8 macro
307 u32 pll0cr = readl(base + CPG_PLL0CR); in rcar_gen2_cpg_clk_register()
Dclk-rcar-gen2.c31 #define CPG_PLL0CR 0x000000d8 macro
332 u32 value = readl(cpg->reg + CPG_PLL0CR); in rcar_gen2_cpg_register_clock()
Drcar-gen3-cpg.c28 #define CPG_PLL0CR 0x00d8 macro
565 value = readl(base + CPG_PLL0CR); in rcar_gen3_cpg_clk_register()