Searched refs:CNL_PORT_CL1CM_DW5 (Results 1 – 3 of 3) sorted by relevance
144 ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5, in cnl_combo_phy_verify_state()165 val = I915_READ(CNL_PORT_CL1CM_DW5); in cnl_combo_phys_init()167 I915_WRITE(CNL_PORT_CL1CM_DW5, val); in cnl_combo_phys_init()
2437 val = I915_READ(CNL_PORT_CL1CM_DW5); in cnl_ddi_vswing_sequence()2439 I915_WRITE(CNL_PORT_CL1CM_DW5, val); in cnl_ddi_vswing_sequence()
1768 #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) macro
