Searched refs:CLK_TOP_UNIVPLL2_D4 (Results 1 – 18 of 18) sorted by relevance
| /Linux-v5.4/Documentation/devicetree/bindings/spi/ |
| D | spi-slave-mt27xx.txt | 19 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
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| D | spi-mt65xx.txt | 30 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
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| /Linux-v5.4/include/dt-bindings/clock/ |
| D | mt8135-clk.h | 49 #define CLK_TOP_UNIVPLL2_D4 38 macro
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| D | mt7629-clk.h | 55 #define CLK_TOP_UNIVPLL2_D4 45 macro
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| D | mt7622-clk.h | 49 #define CLK_TOP_UNIVPLL2_D4 37 macro
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| D | mt6797-clk.h | 73 #define CLK_TOP_UNIVPLL2_D4 63 macro
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| D | mt8173-clk.h | 78 #define CLK_TOP_UNIVPLL2_D4 68 macro
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| D | mt2712-clk.h | 62 #define CLK_TOP_UNIVPLL2_D4 31 macro
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| D | mt2701-clk.h | 40 #define CLK_TOP_UNIVPLL2_D4 30 macro
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| /Linux-v5.4/arch/arm64/boot/dts/mediatek/ |
| D | mt2712e.dtsi | 500 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
579 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
592 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
605 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
618 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
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| /Linux-v5.4/arch/arm/boot/dts/ |
| D | mt7629.dtsi | 310 <&topckgen CLK_TOP_UNIVPLL2_D4>,
371 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
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| /Linux-v5.4/drivers/clk/mediatek/ |
| D | clk-mt8135.c | 68 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
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| D | clk-mt7629.c | 423 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
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| D | clk-mt6797.c | 54 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
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| D | clk-mt7622.c | 415 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
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| D | clk-mt2701.c | 89 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
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| D | clk-mt2712.c | 108 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
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| D | clk-mt8173.c | 113 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
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