Searched refs:CLK_TOP_UNIVPLL1_D4 (Results 1 – 15 of 15) sorted by relevance
| /Linux-v5.4/Documentation/devicetree/bindings/spi/ |
| D | spi-slave-mt27xx.txt | 18 - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.
|
| /Linux-v5.4/include/dt-bindings/clock/ |
| D | mt8135-clk.h | 44 #define CLK_TOP_UNIVPLL1_D4 33 macro
|
| D | mt7629-clk.h | 51 #define CLK_TOP_UNIVPLL1_D4 41 macro
|
| D | mt7622-clk.h | 45 #define CLK_TOP_UNIVPLL1_D4 33 macro
|
| D | mt6797-clk.h | 69 #define CLK_TOP_UNIVPLL1_D4 59 macro
|
| D | mt8173-clk.h | 74 #define CLK_TOP_UNIVPLL1_D4 64 macro
|
| D | mt2712-clk.h | 58 #define CLK_TOP_UNIVPLL1_D4 27 macro
|
| D | mt2701-clk.h | 37 #define CLK_TOP_UNIVPLL1_D4 27 macro
|
| /Linux-v5.4/drivers/clk/mediatek/ |
| D | clk-mt8135.c | 62 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
|
| D | clk-mt7629.c | 419 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
|
| D | clk-mt6797.c | 50 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
|
| D | clk-mt7622.c | 411 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
|
| D | clk-mt2701.c | 85 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
|
| D | clk-mt2712.c | 100 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
|
| D | clk-mt8173.c | 109 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4),
|
