Home
last modified time | relevance | path

Searched refs:CLK_TOP_UART_SEL (Results 1 – 14 of 14) sorted by relevance

/Linux-v5.4/include/dt-bindings/clock/
Dmt8135-clk.h88 #define CLK_TOP_UART_SEL 77 macro
Dmt7629-clk.h91 #define CLK_TOP_UART_SEL 81 macro
Dmt7622-clk.h76 #define CLK_TOP_UART_SEL 64 macro
Dmt8173-clk.h101 #define CLK_TOP_UART_SEL 91 macro
Dmt2712-clk.h138 #define CLK_TOP_UART_SEL 107 macro
Dmt2701-clk.h98 #define CLK_TOP_UART_SEL 87 macro
/Linux-v5.4/arch/arm/boot/dts/
Dmt7629.dtsi216 clocks = <&topckgen CLK_TOP_UART_SEL>,
227 clocks = <&topckgen CLK_TOP_UART_SEL>,
238 clocks = <&topckgen CLK_TOP_UART_SEL>,
/Linux-v5.4/arch/arm64/boot/dts/mediatek/
Dmt7622.dtsi389 clocks = <&topckgen CLK_TOP_UART_SEL>,
400 clocks = <&topckgen CLK_TOP_UART_SEL>,
411 clocks = <&topckgen CLK_TOP_UART_SEL>,
422 clocks = <&topckgen CLK_TOP_UART_SEL>,
587 clocks = <&topckgen CLK_TOP_UART_SEL>,
/Linux-v5.4/drivers/clk/mediatek/
Dclk-mt8135.c373 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
Dclk-mt7629.c505 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
Dclk-mt7622.c535 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
Dclk-mt2701.c505 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
Dclk-mt2712.c756 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
Dclk-mt8173.c553 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),