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Searched refs:CLK_TOP_PWM_SEL (Results 1 – 16 of 16) sorted by relevance

/Linux-v5.4/include/dt-bindings/clock/
Dmt7629-clk.h87 #define CLK_TOP_PWM_SEL 77 macro
Dmt8516-clk.h188 #define CLK_TOP_PWM_SEL 156 macro
Dmt7622-clk.h72 #define CLK_TOP_PWM_SEL 60 macro
Dmt8173-clk.h96 #define CLK_TOP_PWM_SEL 86 macro
Dmt2712-clk.h133 #define CLK_TOP_PWM_SEL 102 macro
Dmt2701-clk.h94 #define CLK_TOP_PWM_SEL 83 macro
/Linux-v5.4/Documentation/devicetree/bindings/pwm/
Dpwm-mediatek.txt31 clocks = <&topckgen CLK_TOP_PWM_SEL>,
/Linux-v5.4/drivers/clk/mediatek/
Dclk-mt7629.c496 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
Dclk-mt8516.c419 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
Dclk-mt7622.c525 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
Dclk-mt2701.c497 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
Dclk-mt2712.c745 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
Dclk-mt8173.c547 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
/Linux-v5.4/arch/arm64/boot/dts/mediatek/
Dmt7622.dtsi432 clocks = <&topckgen CLK_TOP_PWM_SEL>,
Dmt2712e.dtsi426 clocks = <&topckgen CLK_TOP_PWM_SEL>,
/Linux-v5.4/arch/arm/boot/dts/
Dmt7623.dtsi446 clocks = <&topckgen CLK_TOP_PWM_SEL>,