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Searched refs:CLK_TOP_MUX_AUD_1 (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/sound/soc/mediatek/mt8183/
Dmt8183-afe-clk.c30 CLK_TOP_MUX_AUD_1, enumerator
69 [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
237 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
240 __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret); in apll1_mux_setting()
243 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
247 __func__, aud_clks[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
278 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
282 __func__, aud_clks[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
286 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
297 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
[all …]
/Linux-v5.4/include/dt-bindings/clock/
Dmt6797-clk.h37 #define CLK_TOP_MUX_AUD_1 27 macro
Dmt8183-clk.h55 #define CLK_TOP_MUX_AUD_1 19 macro
/Linux-v5.4/drivers/clk/mediatek/
Dclk-mt6797.c365 MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
Dclk-mt8183.c652 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel",