Home
last modified time | relevance | path

Searched refs:CLK_TOP_MEM_SEL (Results 1 – 12 of 12) sorted by relevance

/Linux-v5.4/include/dt-bindings/clock/
Dmt8135-clk.h89 #define CLK_TOP_MEM_SEL 78 macro
Dmt7629-clk.h84 #define CLK_TOP_MEM_SEL 74 macro
Dmt7622-clk.h69 #define CLK_TOP_MEM_SEL 57 macro
Dmt8173-clk.h93 #define CLK_TOP_MEM_SEL 83 macro
Dmt2712-clk.h131 #define CLK_TOP_MEM_SEL 100 macro
Dmt2701-clk.h89 #define CLK_TOP_MEM_SEL 78 macro
/Linux-v5.4/drivers/clk/mediatek/
Dclk-mt7629.c489 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
595 clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]); in mtk_topckgen_init()
Dclk-mt7622.c517 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
641 clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]); in mtk_topckgen_init()
Dclk-mt8173.c543 MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1),
918 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_MEM_SEL]); in mtk_clk_enable_critical()
Dclk-mt8135.c375 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
Dclk-mt2701.c490 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
Dclk-mt2712.c740 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,