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Searched refs:CLK_TOP_AXI_SEL (Results 1 – 16 of 16) sorted by relevance

/Linux-v5.4/include/dt-bindings/clock/
Dmt8135-clk.h73 #define CLK_TOP_AXI_SEL 62 macro
Dmt7629-clk.h83 #define CLK_TOP_AXI_SEL 73 macro
Dmt7622-clk.h68 #define CLK_TOP_AXI_SEL 56 macro
Dmt8173-clk.h92 #define CLK_TOP_AXI_SEL 82 macro
Dmt2712-clk.h130 #define CLK_TOP_AXI_SEL 99 macro
Dmt2701-clk.h90 #define CLK_TOP_AXI_SEL 79 macro
/Linux-v5.4/arch/arm/boot/dts/
Dmt7629.dtsi254 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
306 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
369 <&topckgen CLK_TOP_AXI_SEL>,
/Linux-v5.4/drivers/clk/mediatek/
Dclk-mt7629.c487 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
594 clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); in mtk_topckgen_init()
Dclk-mt7622.c515 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
640 clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); in mtk_topckgen_init()
Dclk-mt8135.c352 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
Dclk-mt2701.c488 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
Dclk-mt2712.c738 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
Dclk-mt8173.c542 MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
/Linux-v5.4/arch/arm64/boot/dts/mediatek/
Dmt7622.dtsi252 <&topckgen CLK_TOP_AXI_SEL>;
697 <&topckgen CLK_TOP_AXI_SEL>;
Dmt2712e.dtsi652 <&topckgen CLK_TOP_AXI_SEL>,
663 <&topckgen CLK_TOP_AXI_SEL>,
Dmt8173.dtsi819 <&topckgen CLK_TOP_AXI_SEL>;
829 <&topckgen CLK_TOP_AXI_SEL>;