Home
last modified time | relevance | path

Searched refs:CLK_TOP_APLL_SEL (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.4/include/dt-bindings/clock/
Dmt8135-clk.h102 #define CLK_TOP_APLL_SEL 91 macro
Dmt2712-clk.h170 #define CLK_TOP_APLL_SEL 139 macro
Dmt2701-clk.h107 #define CLK_TOP_APLL_SEL 96 macro
/Linux-v5.4/drivers/clk/mediatek/
Dclk-mt8135.c393 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
Dclk-mt2701.c537 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
Dclk-mt2712.c828 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel",