Searched refs:CLK_TOP_APLL12_DIV0 (Results 1 – 7 of 7) sorted by relevance
| /Linux-v5.4/sound/soc/mediatek/mt8183/ |
| D | mt8183-afe-clk.c | 44 CLK_TOP_APLL12_DIV0, enumerator
83 [CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
514 .div_clk_id = CLK_TOP_APLL12_DIV0,
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| /Linux-v5.4/include/dt-bindings/clock/ |
| D | mt8516-clk.h | 151 #define CLK_TOP_APLL12_DIV0 119 macro
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| D | mt8183-clk.h | 158 #define CLK_TOP_APLL12_DIV0 122 macro
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| D | mt6779-clk.h | 138 #define CLK_TOP_APLL12_DIV0 128 macro
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| /Linux-v5.4/drivers/clk/mediatek/ |
| D | clk-mt8516.c | 666 GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
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| D | clk-mt6779.c | 827 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
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| D | clk-mt8183.c | 736 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel",
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