Searched refs:CLK_SCLK_MPLL (Results 1 – 4 of 4) sorted by relevance
| /Linux-v5.4/arch/arm/boot/dts/ |
| D | exynos4210-trats.dts | 210 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
218 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
226 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
234 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
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| D | exynos4210-universal_c210.dts | 220 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
228 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
236 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
244 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
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| /Linux-v5.4/include/dt-bindings/clock/ |
| D | exynos4.h | 21 #define CLK_SCLK_MPLL 9 macro
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| /Linux-v5.4/drivers/clk/samsung/ |
| D | clk-exynos4.c | 463 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
540 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
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