Searched refs:CLK_RESET_PLLX_BASE (Results 1 – 2 of 2) sorted by relevance
| /Linux-v5.4/arch/arm/mach-tegra/ |
| D | sleep-tegra30.S | 56 #define CLK_RESET_PLLX_BASE 0xe0 macro
348 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
361 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
371 pll_locked r1, r0, CLK_RESET_PLLX_BASE
642 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
644 str r0, [r5, #CLK_RESET_PLLX_BASE]
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| /Linux-v5.4/drivers/clk/tegra/ |
| D | clk-tegra30.c | 122 #define CLK_RESET_PLLX_BASE 0xe0 macro
1160 readl(clk_base + CLK_RESET_PLLX_BASE); in tegra30_cpu_clock_suspend()
1187 clk_base + CLK_RESET_PLLX_BASE); in tegra30_cpu_clock_resume()
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