Searched refs:CLK_PPMULCD1 (Results 1 – 3 of 3) sorted by relevance
223 #define CLK_PPMULCD1 409 /* Exynos4210 only */ macro
187 clocks = <&clock CLK_PPMULCD1>;
923 GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
