Searched refs:CLK_MM_DISP_WDMA0 (Results 1 – 12 of 12) sorted by relevance
| /Linux-v5.4/drivers/clk/mediatek/ |
| D | clk-mt8183-mm.c | 61 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
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| D | clk-mt6779-mm.c | 60 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
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| D | clk-mt6797-mm.c | 66 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
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| D | clk-mt2712-mm.c | 83 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
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| D | clk-mt8173.c | 808 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
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| /Linux-v5.4/include/dt-bindings/clock/ |
| D | mt6797-clk.h | 236 #define CLK_MM_DISP_WDMA0 22 macro
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| D | mt8173-clk.h | 269 #define CLK_MM_DISP_WDMA0 21 macro
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| D | mt2712-clk.h | 322 #define CLK_MM_DISP_WDMA0 21 macro
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| D | mt8183-clk.h | 333 #define CLK_MM_DISP_WDMA0 24 macro
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| D | mt6779-clk.h | 365 #define CLK_MM_DISP_WDMA0 25 macro
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| /Linux-v5.4/Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,disp.txt | 129 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
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| /Linux-v5.4/arch/arm64/boot/dts/mediatek/ |
| D | mt8173.dtsi | 1041 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
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