Searched refs:CLK_BASE (Results 1 – 15 of 15) sorted by relevance
| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr_internal.h | 80 #define CLK_BASE(inst) \ macro
84 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr_clk.c | 44 CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
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| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | navi10_reg_init.c | 50 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); in navi10_reg_base_init()
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| D | navi12_reg_init.c | 50 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); in navi12_reg_base_init()
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| D | navi14_reg_init.c | 50 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); in navi14_reg_base_init()
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| D | vega10_reg_init.c | 54 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); in vega10_reg_base_init()
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| D | vega20_reg_init.c | 52 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); in vega20_reg_base_init()
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| /Linux-v5.4/drivers/gpu/drm/amd/include/ |
| D | navi10_ip_offset.h | 43 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x0001… variable
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| D | navi12_ip_offset.h | 46 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, variable
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| D | navi14_ip_offset.h | 46 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, variable
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| D | vega20_ip_offset.h | 45 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x0001… variable
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| D | vega10_ip_offset.h | 203 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } }, variable
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| D | renoir_ip_offset.h | 53 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } }, variable
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| D | arct_ip_offset.h | 47 static const struct IP_BASE CLK_BASE ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, … variable
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 53 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
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