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Searched refs:CHL_INT0 (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.4/drivers/scsi/hisi_sas/
Dhisi_sas_v1_hw.c157 #define CHL_INT0 (PORT_BASE + 0x1b0) macro
1396 u32 chl_int0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); in int_phyup_v1_hw()
1399 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, chl_int0); in int_phyup_v1_hw()
1450 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); in int_abnormal_v1_hw()
1479 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, irq_value); in int_abnormal_v1_hw()
1712 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT0); in interrupt_openall_v1_hw()
1713 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, val); in interrupt_openall_v1_hw()
Dhisi_sas_v3_hw.c248 #define CHL_INT0 (PORT_BASE + 0x1b4) macro
612 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); in init_reg_v3_hw()
1532 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, in phy_up_v3_hw()
1560 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); in phy_down_v3_hw()
1578 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, in phy_bcast_v3_hw()
1597 CHL_INT0); in int_phy_up_down_bcast_v3_hw()
1795 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); in handle_chl_int0_v3_hw()
1800 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, in handle_chl_int0_v3_hw()
2758 HISI_SAS_DEBUGFS_REG(CHL_INT0),
Dhisi_sas_v2_hw.c223 #define CHL_INT0 (PORT_BASE + 0x1b4) macro
1246 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); in init_reg_v2_hw()
2704 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, in phy_up_v2_hw()
2748 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); in phy_down_v2_hw()
2766 CHL_INT0); in int_phy_updown_v2_hw()
2826 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, in phy_bcast_v2_hw()
2875 CHL_INT0); in int_chnl_int_v2_hw()
2922 CHL_INT0, irq_value0 in int_chnl_int_v2_hw()