| /Linux-v5.4/drivers/gpu/drm/radeon/ |
| D | rv740d.h | 26 #define CG_SPLL_FUNC_CNTL 0x600 macro
|
| D | rv730d.h | 26 #define CG_SPLL_FUNC_CNTL 0x600 macro
|
| D | rs780d.h | 26 #define CG_SPLL_FUNC_CNTL 0x600 macro
|
| D | rs780_dpm.c | 213 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in rs780_preset_starting_fbdiv()
989 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_debugfs_print_current_performance_level()
1011 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_get_current_sclk()
|
| D | rv740_dpm.c | 289 RREG32(CG_SPLL_FUNC_CNTL); in rv740_read_clock_registers()
|
| D | r600_dpm.c | 322 WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN); in r600_enable_spll_bypass()
324 WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN); in r600_enable_spll_bypass()
332 if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS) in r600_wait_for_spll_change()
|
| D | rv730_dpm.c | 202 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
|
| D | rv770d.h | 89 #define CG_SPLL_FUNC_CNTL 0x600 macro
|
| D | si.c | 3991 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_set_clk_bypass_mode()
3993 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_set_clk_bypass_mode()
4022 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
4024 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
4026 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
4028 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
|
| D | nid.h | 538 #define CG_SPLL_FUNC_CNTL 0x600 macro
|
| D | sid.h | 85 #define CG_SPLL_FUNC_CNTL 0x600 macro
|
| D | cikd.h | 248 #define CG_SPLL_FUNC_CNTL 0xC0500140 macro
|
| D | evergreend.h | 74 #define CG_SPLL_FUNC_CNTL 0x600 macro
|
| D | r600d.h | 1270 #define CG_SPLL_FUNC_CNTL 0x600 macro
|
| D | rv770_dpm.c | 1521 RREG32(CG_SPLL_FUNC_CNTL); in rv770_read_clock_registers()
|
| D | ni_dpm.c | 1185 ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in ni_read_clock_registers()
|
| D | si_dpm.c | 3572 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in si_read_clock_registers()
|
| D | ci_dpm.c | 1875 RREG32_SMC(CG_SPLL_FUNC_CNTL); in ci_read_clock_registers()
|
| /Linux-v5.4/drivers/gpu/drm/amd/powerplay/smumgr/ |
| D | fiji_smumgr.c | 887 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_calculate_sclk_params()
889 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_calculate_sclk_params()
1347 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_populate_smc_acpi_level()
1349 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_populate_smc_acpi_level()
|
| D | iceland_smumgr.c | 826 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in iceland_calculate_sclk_params()
828 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in iceland_calculate_sclk_params()
1462 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); in iceland_populate_smc_acpi_level()
1464 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); in iceland_populate_smc_acpi_level()
|
| D | ci_smumgr.c | 325 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in ci_calculate_sclk_params()
327 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in ci_calculate_sclk_params()
1414 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); in ci_populate_smc_acpi_level()
1416 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); in ci_populate_smc_acpi_level()
|
| D | tonga_smumgr.c | 569 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in tonga_calculate_sclk_params()
571 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in tonga_calculate_sclk_params()
1210 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in tonga_populate_smc_acpi_level()
1212 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in tonga_populate_smc_acpi_level()
|
| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | sid.h | 87 #define CG_SPLL_FUNC_CNTL 0x180 macro
|
| D | si_dpm.c | 4032 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in si_read_clock_registers()
|
