| /Linux-v5.4/arch/arm/plat-omap/ |
| D | dma.c | 208 ccr = p->dma_read(CCR, lch); in omap_set_dma_priority()
213 p->dma_write(ccr, CCR, lch); in omap_set_dma_priority()
232 ccr = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
236 p->dma_write(ccr, CCR, lch); in omap_set_dma_transfer_params()
248 val = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
273 p->dma_write(val, CCR, lch); in omap_set_dma_transfer_params()
323 l = p->dma_read(CCR, lch); in omap_set_dma_src_params()
326 p->dma_write(l, CCR, lch); in omap_set_dma_src_params()
423 l = p->dma_read(CCR, lch); in omap_set_dma_dest_params()
426 p->dma_write(l, CCR, lch); in omap_set_dma_dest_params()
[all …]
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| /Linux-v5.4/drivers/dma/ |
| D | txx9dmac.h | 77 TXX9_DMA_REG32(CCR); /* Channel Control Register */
87 u32 CCR; member
278 desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
280 desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
294 desc->hwdesc.CCR = ccr; in txx9dmac_desc_set_nosimple()
298 desc->hwdesc32.CCR = ccr; in txx9dmac_desc_set_nosimple()
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| D | txx9dmac.c | 295 channel64_readl(dc, CCR), in txx9dmac_dump_regs()
307 channel32_readl(dc, CCR), in txx9dmac_dump_regs()
313 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST); in txx9dmac_reset_chan()
326 channel_writel(dc, CCR, 0); in txx9dmac_reset_chan()
365 channel64_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
386 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
391 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
480 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
493 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
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| D | pl330.c | 339 CCR, enumerator
1262 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); in _dregs()
1411 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); in _setup_req()
|
| /Linux-v5.4/arch/arm/mach-imx/ |
| D | pm-imx6.c | 28 #define CCR 0x0 macro
252 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
255 writel_relaxed(val, ccm_base + CCR); in imx6_enable_rbc()
258 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
261 writel(val, ccm_base + CCR); in imx6_enable_rbc()
285 val = readl_relaxed(ccm_base + CCR); in imx6q_enable_wb()
288 writel_relaxed(val, ccm_base + CCR); in imx6q_enable_wb()
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| /Linux-v5.4/drivers/clocksource/ |
| D | timer-atmel-tcb.c | 101 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR)); in tc_clksrc_resume()
169 writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); in tc_shutdown()
218 ATMEL_TC_REG(2, CCR)); in tc_set_periodic()
228 tcaddr + ATMEL_TC_REG(2, CCR)); in tc_next_event()
319 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_dual_chan()
327 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); in tcb_setup_dual_chan()
343 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_single_chan()
|
| /Linux-v5.4/arch/arm/mach-omap1/ |
| D | dma.c | 57 [CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
214 l = dma_read(CCR, lch); in omap1_clear_dma()
216 dma_write(l, CCR, lch); in omap1_clear_dma()
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| /Linux-v5.4/drivers/pwm/ |
| D | pwm-atmel-tcb.c | 189 regs + ATMEL_TC_REG(group, CCR)); in atmel_tcb_pwm_disable()
193 ATMEL_TC_REG(group, CCR)); in atmel_tcb_pwm_disable()
277 regs + ATMEL_TC_REG(group, CCR)); in atmel_tcb_pwm_enable()
493 base + ATMEL_TC_REG(i, CCR)); in atmel_tcb_pwm_resume()
|
| /Linux-v5.4/drivers/dma/ti/ |
| D | omap-dma.c | 422 omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); in omap_dma_start()
434 val = omap_dma_chan_read(c, CCR); in omap_dma_drain_chan()
460 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
469 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
471 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
482 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
552 omap_dma_chan_write(c, CCR, d->ccr); in omap_dma_start_desc()
857 uint32_t ccr = omap_dma_chan_read(c, CCR); in omap_dma_tx_status()
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| /Linux-v5.4/sound/soc/dwc/ |
| D | local.h | 24 #define CCR 0x010 macro
|
| D | dwc-i2s.c | 282 i2s_write_reg(dev->i2s_base, CCR, dev->ccr); in dw_i2s_hw_params()
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| /Linux-v5.4/arch/arm/mach-omap2/ |
| D | dma.c | 57 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
|
| /Linux-v5.4/sound/pci/emu10k1/ |
| D | emu10k1_callback.c | 421 snd_emu10k1_ptr_write(hw, CCR, ch, 0x1c << 16); in start_voice()
434 snd_emu10k1_ptr_write(hw, CCR, ch, val); in start_voice()
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| D | emu10k1_main.c | 66 snd_emu10k1_ptr_write(emu, CCR, ch, 0); in snd_emu10k1_voice_init()
2053 CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP,
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| /Linux-v5.4/include/linux/ |
| D | omap-dma.h | 154 CSDP, CCR, CICR, CSR, enumerator
|
| /Linux-v5.4/Documentation/parisc/ |
| D | registers.rst | 18 CR10 (CCR) lazy FPU saving*
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| /Linux-v5.4/include/sound/ |
| D | emu10k1.h | 424 #define CCR 0x09 /* Cache control register */ macro
|
| /Linux-v5.4/Documentation/powerpc/ |
| D | transactional_memory.rst | 63 Checkpointed registers include all GPRs, FPRs, VRs/VSRs, LR, CCR/CR, CTR, FPCSR
|
| /Linux-v5.4/drivers/tty/ |
| D | synclink_gt.c | 399 #define CCR 0x89 /* clock control */ macro
3906 wr_reg8(info, CCR, 0x49); in enable_loopback()
4189 wr_reg8(info, CCR, 0x69); in async_mode()
4402 wr_reg8(info, CCR, (unsigned char)val); in sync_mode()
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| D | synclink.c | 341 #define CCR 0x06 /* Channel Control Register */ macro
5102 usc_OutReg( info, CCR, RegValue ); in usc_set_sdlc_mode()
6018 usc_OutReg( info, CCR, 0x0100 ); in usc_loopback_frame()
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| /Linux-v5.4/drivers/video/fbdev/ |
| D | imsttfb.c | 93 CCR = 0x00000008L,
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