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Searched refs:CACHE_MODE_0_GEN7 (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Dmmio_context.c63 {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
95 {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
Dhandlers.c1921 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, in init_generic_mmio_info()
/Linux-v5.4/drivers/gpu/drm/i915/gt/
Dintel_workarounds.c219 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); in gen8_ctx_workarounds_init()
/Linux-v5.4/drivers/gpu/drm/i915/
Dintel_pm.c9354 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in hsw_init_clock_gating()
9357 I915_WRITE(CACHE_MODE_0_GEN7, in hsw_init_clock_gating()
9406 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in ivb_init_clock_gating()
9450 I915_WRITE(CACHE_MODE_0_GEN7, in ivb_init_clock_gating()
9498 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in vlv_init_clock_gating()
Di915_reg.h2873 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ macro