Searched refs:Bytes (Results 1 – 25 of 30) sorted by relevance
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15 * Bytes 0x0 Write panic event to the reg when guest OS panics.16 * Bytes 0x1 Reserved.
21 andi $r1, $r1, #3 ! Bytes less than a word to copy39 sub $r0, $r5, $r0 ! Bytes left to copy
720 256 Bytes of data in this page722 256 Bytes of data in this page724 256 Bytes of data in this page731 256 Bytes of data in this page733 256 Bytes of data in this page752 256 Bytes of data in this page754 256 Bytes data in this page756 256 Bytes of data in this page758 256 Bytes of data in this page760 256 Bytes of data in this page[all …]
23 * Bytes 0x0 to 0x7 cover the data register.24 * Bytes 0x8 to 0x9 cover the selector register.
47 |Device || Offset Bytes | Sectors | MiB || Size Bytes | Sectors | MiB|
1465 rbytes Bytes read1466 wbytes Bytes written1469 dbytes Bytes discarded
26 4 wReportDescLength 00B2 Report Descriptor is 178 Bytes (0x00B2)29 10 wMaxInputLength 0053 Input Report is 80 Bytes + 2
28 CDROMREADMODE2 Read CDROM mode 2 data (2336 Bytes)30 CDROMREADMODE1 Read CDROM mode 1 data (2048 Bytes)43 CDROMREADRAW read data in raw mode (2352 Bytes)440 read data in raw mode (2352 Bytes)480 Read CDROM mode 1 data (2048 Bytes)491 Read CDROM mode 2 data (2336 Bytes)
30 rows. Bytes are stored in memory in little endian order. They are
32 n/2 blue or red samples, with alternating red and blue rows. Bytes are
33 and n/2 blue or red samples, with alternating red and blue rows. Bytes
109 Description: Bytes available to read116 Description: Bytes available to write
31 Function Raw Bytes
31 values inside packets are encoded using little-endian. Bytes whose roles are114 Val c = X and Y axes. Bytes 05 must contain 60
85 FSP uses 2 packets (8 Bytes) to represent Absolute Position.
147 * addr2 - addr <= 8 Bytes.
48 string (the rest of the event). Bytes 1, 2, and 3 are the normal
98 int "Size in Mega Bytes"
171 Bytes b4 0xc90f6d10: 00 00 00 00 00 00 00 00 5a 5a 5a 5a 5a 5a 5a 5a ........ZZZZZZZZ227 Bytes b4 <address> : <bytes>
272 U8 Bytes[4]; member295 U8 Bytes[8]; member
1073 Setting ARM L1 cache line size to 64 Bytes.1078 Setting ARM L1 cache line size to 128 Bytes.
351 U8 Bytes[4]; member
667 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
501 # output r13 Bytes859 # output encrypted Bytes
750 # output encrypted Bytes
