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Searched refs:BLK_CONTROL (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/arm/display/komeda/d71/
Dd71_dev.c278 malidp_write32_mask(d71->gcu_addr, BLK_CONTROL, 0x7, opmode); in d71_change_opmode()
280 ret = dp_wait_cond(((malidp_read32(d71->gcu_addr, BLK_CONTROL) & 0x7) == opmode), in d71_change_opmode()
301 malidp_write32_mask(gcu, BLK_CONTROL, in d71_reset()
304 ret = dp_wait_cond(!(malidp_read32(gcu, BLK_CONTROL) & GCU_CONTROL_SRST), in d71_reset()
527 malidp_write32_mask(reg, BLK_CONTROL, 0x7, TBU_CONNECT_MODE); in d71_connect_iommu()
533 malidp_write32_mask(reg, BLK_CONTROL, 0x7, INACTIVE_MODE); in d71_connect_iommu()
551 malidp_write32_mask(reg, BLK_CONTROL, 0x7, TBU_DISCONNECT_MODE); in d71_disconnect_iommu()
557 malidp_write32_mask(reg, BLK_CONTROL, 0x7, INACTIVE_MODE); in d71_disconnect_iommu()
Dd71_component.c194 malidp_write32_mask(c->reg, BLK_CONTROL, L_EN, 0); in d71_layer_disable()
266 malidp_write32_mask(reg, BLK_CONTROL, ctrl_mask, ctrl); in d71_layer_update()
394 malidp_write32_mask(reg, BLK_CONTROL, mask, ctrl); in d71_wb_layer_update()
429 malidp_write32_mask(c->reg, BLK_CONTROL, L_EN, 0); in d71_wb_layer_disable()
471 malidp_write32(reg, BLK_CONTROL, 0); in d71_component_disable()
700 malidp_write32(reg, BLK_CONTROL, ctrl); in d71_scaler_update()
763 malidp_write32(c->reg, BLK_CONTROL, 0); in d71_scaler_init()
818 malidp_write32(reg, BLK_CONTROL, BLK_CTRL_EN); in d71_splitter_update()
830 get_values_from_reg(c->reg, BLK_CONTROL, 3, v); in d71_splitter_dump()
884 malidp_write32(reg, BLK_CONTROL, BLK_CTRL_EN); in d71_merger_update()
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Dd71_regs.h22 #define BLK_CONTROL 0x0D0 macro