Searched refs:BIT_5 (Results 1 – 19 of 19) sorted by relevance
22 #define BIT_5 0x20 macro125 #define ISP_CFG0_1040C BIT_5 /* ISP1040C */128 #define ISP_CFG1_F64 BIT_4|BIT_5 /* 128-byte FIFO threshold */129 #define ISP_CFG1_F32 BIT_5 /* 128-byte FIFO threshold */310 #define TP_PPR BIT_5 /* PPR */
445 return BIT_5; in qla1280_data_direction()449 return BIT_5 | BIT_6; in qla1280_data_direction()1915 status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_5 | in qla1280_init_rings()2184 cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6); in qla1280_nvram_config()2257 mb[1] |= BIT_5; in qla1280_nvram_config()2262 mb[2] |= BIT_5; in qla1280_nvram_config()3913 if ((mb[2] & BIT_5) && ((mb[6] >> 8) & 0xff) >= 2) in qla1280_get_target_parameters()
24 #define FO2_ENABLE_SEL_CLASS2 BIT_541 #define PDF_FCP2_CONF BIT_5844 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */845 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */1018 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)1059 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */1340 VP_FLAGS_NAME_VALID = BIT_5,
85 #define BIT_5 0x20 macro331 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */767 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */1078 #define FO1_DISABLE_100MS_LOS_WAIT BIT_51099 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_51252 #define MBX_5 BIT_51826 #define CF_READ BIT_51894 #define PO_DISABLE_INCR_REF_TAG BIT_51986 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */2404 #define NVME_PRLI_SP_INITIATOR BIT_5[all …]
85 #define OF_EXPL_CONF BIT_5 /* Explicit Confirmation Requested */467 #define CTIO7_FLAGS_EXPLICIT_CONFORM BIT_5734 #define NOTIFY_ACK_CLEAR_LIP_RESET BIT_5833 TRC_XMIT_STATUS = BIT_5,
3766 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; in qla2x00_update_fw_options()3773 ha->fw_options[10] |= BIT_5 | in qla2x00_update_fw_options()3779 (BIT_7 | BIT_6 | BIT_5)) >> 5; in qla2x00_update_fw_options()3784 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; in qla2x00_update_fw_options()3791 ha->fw_options[11] |= BIT_5 | in qla2x00_update_fw_options()4499 nv->firmware_options[1] = BIT_7 | BIT_5; in qla2x00_nvram_config()4500 nv->add_firmware_options[0] = BIT_5; in qla2x00_nvram_config()4501 nv->add_firmware_options[1] = BIT_5 | BIT_4; in qla2x00_nvram_config()4506 nv->firmware_options[1] = BIT_7 | BIT_5; in qla2x00_nvram_config()4507 nv->add_firmware_options[0] = BIT_5; in qla2x00_nvram_config()[all …]
744 options |= BIT_5; in qla25xx_create_req_que()864 options |= BIT_5; in qla25xx_create_rsp_que()
738 mcp->in_mb |= BIT_5; in qla2x00_execute_fw()2212 mcp->mb[1] |= BIT_5; in qla24xx_link_initialize()4098 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; in qla24xx_modify_vp_config()6101 if (!(subcode & (BIT_2 | BIT_5))) in qla83xx_access_control()6114 if (subcode & BIT_5) in qla83xx_access_control()6402 if ((pd->prli_svc_param_word_3[0] & BIT_5) == 0) in __qla24xx_parse_gpdb()
6871 nv->firmware_options_1 |= cpu_to_le32(BIT_5); in qlt_24xx_config_nvram_stage1()6898 tmp = ~(BIT_4|BIT_5|BIT_6); in qlt_24xx_config_nvram_stage1()6977 nv->firmware_options_1 |= cpu_to_le32(BIT_5); in qlt_81xx_config_nvram_stage1()7002 tmp = ~(BIT_4|BIT_5|BIT_6); in qlt_81xx_config_nvram_stage1()7064 vpmod->options_idx1 &= ~BIT_5; in qlt_modify_vp_config()
2148 if ((flash_data & BIT_5) && cnt > 2) in qla2x00_poll_flash()
1745 } else if (iop[0] & BIT_5) in qla24xx_logio_entry()
1367 arg1 |= (BIT_2 | BIT_5); in qlcnic_config_switch_port()1371 arg1 |= (BIT_3 | BIT_5); in qlcnic_config_switch_port()1422 esw_cfg->host_vlan_tag = !!(arg1 & BIT_5); in qlcnic_get_eswitch_port_config()
201 #define BIT_5 0x20 macro
29 #define QLCNIC_DUMP_RD_SAVE BIT_5
926 #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5
389 if (status & BIT_5) in qlcnic_sriov_get_vf_vport_info()
368 #define QLCNIC_ENCAP_DO_L4_CSUM BIT_5
87 #define BIT_5 0x20 macro
3639 SET_BITVAL(sess->discovery_logout_en, options, BIT_5); in qla4xxx_copy_to_fwddb_param()3648 SET_BITVAL(conn->tcp_nagle_disable, options, BIT_5); in qla4xxx_copy_to_fwddb_param()
