Searched refs:BIT25 (Results 1 – 15 of 15) sorted by relevance
209 #define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */231 #define IMR_BCNDMAINT5_8723B BIT25 /* Beacon DMA Interrupt 5 */
564 #define HSIMR_GPIO9_INT_EN BIT25573 #define HSISR_GPIO9_INT BIT25779 #define IMR_BCNDOK8 BIT25 /* Beacon Queue DMA OK Interrup 8 */827 #define PHIMR_TXBCNOK BIT25878 #define UHIMR_TXBCNOK BIT25939 #define IMR_TBDOK_88E BIT25 /* Transmit Beacon0 OK */962 #define IMR_BCNDMAINT5_88E BIT25 /* Beacon DMA Interrupt 5 */1026 #define RCR_RSVD_BIT25 BIT25 /* Reserved */1584 #define SDIO_HIMR_ATIMEND_MSK BIT251610 #define SDIO_HISR_ATIMEND BIT25
46 #define BIT25 0x02000000 macro
66 #define DYNAMIC_RF_RX_GAIN_TRACK BIT25/* ODM_RF_RX_GAIN_TRACK */
391 #define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */413 #define IMR_BCNDMAINT5_8723B BIT25 /* Beacon DMA Interrupt 5 */441 #define RCR_TCPOFLD_EN BIT25 /* Enable TCP checksum offload */
64 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 1); in odm_InbandNoise_Monitor_NSeries()75 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 0); in odm_InbandNoise_Monitor_NSeries()
82 #define ODM_COMP_RX_GAIN_TRACK BIT25
444 ODM_RF_RX_GAIN_TRACK = BIT25,
56 #define BIT25 0x02000000 macro
81 #define BIT25 0x02000000 macro262 #define EPN_MODE (BIT25 + BIT24)265 #define EPN_ISO BIT25
35 #define BIT25 0x02000000 macro
44 #define BIT25 0x02000000 macro
51 #define BIT25 0x02000000 macro
136 #define RCR_ACKTXBW (BIT24|BIT25)
734 #define LPFC_SLI4_INTR25 BIT25
