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Searched refs:BANK_WIDTH (Results 1 – 15 of 15) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c84 #define BANK_WIDTH(x) ((x) << 14) macro
423 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
431 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
439 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
446 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
458 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
466 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
474 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
486 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
494 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
[all …]
Dgfx_v8_0.c72 #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT) macro
2246 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2250 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2254 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2258 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2262 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2266 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2270 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2274 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2278 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
[all …]
Dgfx_v7_0.c1158 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1162 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1166 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1170 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1174 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1178 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1182 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1186 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
1190 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
1194 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
[all …]
Dcikd.h196 # define BANK_WIDTH(x) ((x) << 0) macro
Dsid.h1204 # define BANK_WIDTH(x) ((x) << 14) macro
Ddce_v8_0.c1894 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
Ddce_v6_0.c1920 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()
Ddce_v10_0.c1973 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
Ddce_v11_0.c2015 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
/Linux-v5.4/drivers/gpu/drm/radeon/
Dsi.c2525 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2534 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2543 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2552 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2561 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2570 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2579 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2588 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2597 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2606 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
[all …]
Dcik.c2449 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2453 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2457 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2461 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2465 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2469 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2473 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2477 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2481 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2485 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
[all …]
Dsid.h1206 # define BANK_WIDTH(x) ((x) << 14) macro
Dcikd.h1260 # define BANK_WIDTH(x) ((x) << 0) macro
/Linux-v5.4/drivers/gpu/drm/amd/include/
Dnavi10_enum.h1744 typedef enum BANK_WIDTH { enum
1749 } BANK_WIDTH; typedef
/Linux-v5.4/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm.c2812 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_plane_buffer_attributes()