Searched refs:B0_XS_CSR (Results 1 – 3 of 3) sorted by relevance
310 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XS_CSR) ; in init_tx()974 outpd(ADDR(B0_XS_CSR),CSR_SET_RESET) ; in init_mac()978 outpd(ADDR(B0_XS_CSR),CSR_CLR_RESET) ; in init_mac()
571 outpd(ADDR(B0_XS_CSR),CSR_START) ; in mac_drv_repair_descr()1662 outpd(ADDR(B0_XS_CSR),CSR_START) ; in hwm_tx_frag()
89 #define B0_XS_CSR 0x007c /* 32 bit BMU control/status reg (s xmit q) */ macro
