Searched refs:B0_XA_CSR (Results 1 – 3 of 3) sorted by relevance
321 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XA_CSR) ; in init_tx()973 outpd(ADDR(B0_XA_CSR),CSR_SET_RESET) ; in init_mac()977 outpd(ADDR(B0_XA_CSR),CSR_CLR_RESET) ; in init_mac()
566 outpd(ADDR(B0_XA_CSR),CSR_START) ; in mac_drv_repair_descr()1659 outpd(ADDR(B0_XA_CSR),CSR_START) ; in hwm_tx_frag()1899 outpd(ADDR(B0_XA_CSR),CSR_START) ; in smt_send_mbuf()
88 #define B0_XA_CSR 0x0078 /* 32 bit BMU control/status reg (a xmit q) */ macro
