Searched refs:AXI_MASTER_CFG_BASE (Results 1 – 2 of 2) sorted by relevance
279 #define AXI_MASTER_CFG_BASE (0x5000) macro1429 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN); in axi_bus_is_idle_v2_hw()1491 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + in disable_phy_v2_hw()1494 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + in disable_phy_v2_hw()1528 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + in disable_phy_v2_hw()3434 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1); in soft_reset_v2_hw()3440 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN); in soft_reset_v2_hw()
309 #define AXI_MASTER_CFG_BASE (0x5000) macro2061 AXI_MASTER_CFG_BASE + in fatal_axi_int_v3_hw()2064 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + in fatal_axi_int_v3_hw()2534 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + in disable_host_v3_hw()2537 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + in disable_host_v3_hw()2541 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + in disable_host_v3_hw()2875 .base_off = AXI_MASTER_CFG_BASE,
