Searched refs:ARC_REG_TLBPD0 (Results 1 – 3 of 3) sorted by relevance
26 #define ARC_REG_TLBPD0 0x405 macro34 #define ARC_REG_TLBPD0 0x460 macro
117 write_aux_reg(ARC_REG_TLBPD0, 0); in __tlb_entry_erase()127 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid); in tlb_entry_lkup()229 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT); in tlb_entry_erase()235 write_aux_reg(ARC_REG_TLBPD0, pd0); in tlb_entry_insert()265 write_aux_reg(ARC_REG_TLBPD0, 0); in local_flush_tlb_all()277 write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ); in local_flush_tlb_all()930 pd0[way] = read_aux_reg(ARC_REG_TLBPD0); in do_tlb_overlap_fault()
262 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid265 sr r3,[ARC_REG_TLBPD0] ; rewrite PD0
