Searched refs:AMDGPU_IRQ_STATE_ENABLE (Results 1 – 25 of 30) sorted by relevance
12
43 AMDGPU_IRQ_STATE_ENABLE, enumerator
306 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_ack_irq()359 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_rcv_irq()
505 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_ack_irq()535 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_rcv_irq()
601 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()617 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
444 state = AMDGPU_IRQ_STATE_ENABLE; in amdgpu_irq_update()
524 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v2_0_set_interrupt_state()
225 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_ecc_interrupt_state()312 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_vm_fault_interrupt_state()
1019 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()1035 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
1126 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()1142 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
1353 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()1369 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
101 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v10_0_vm_fault_interrupt_state()
5489 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()5492 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_gfx_eop_interrupt_state()5541 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_compute_eop_interrupt_state()5559 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_reg_fault_state()5562 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()5578 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_inst_fault_state()5581 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_inst_fault_state()5612 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_cp_ecc_error_state()
3247 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()3276 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_compute_eop_interrupt_state()3310 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_reg_fault_state()3335 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_inst_fault_state()
1078 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v6_0_vm_fault_interrupt_state()
708 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v3_0_set_interrupt_state()
4844 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v10_0_set_gfx_eop_interrupt_state()4897 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v10_0_set_compute_eop_interrupt_state()4992 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v10_0_set_priv_reg_fault_state()4995 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v10_0_set_priv_reg_fault_state()5011 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v10_0_set_priv_inst_fault_state()5014 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v10_0_set_priv_inst_fault_state()
2881 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_crtc_vblank_interrupt_state()2932 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_crtc_vline_interrupt_state()2960 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_hpd_interrupt_state()
4713 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_gfx_eop_interrupt_state()4764 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_compute_eop_interrupt_state()4787 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_priv_reg_fault_state()4812 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_priv_inst_fault_state()
1994 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in sdma_v4_0_set_trap_irq_state()2103 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in sdma_v4_0_set_ecc_irq_state()
2970 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_crtc_vblank_interrupt_state()2999 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_crtc_vline_interrupt_state()3028 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_hpd_irq_state()
3096 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_crtc_vblank_interrupt_state()3125 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_crtc_vline_interrupt_state()3154 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_hpd_irq_state()
1226 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v7_0_vm_fault_interrupt_state()
1017 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v4_0_set_interrupt_state()
1398 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v8_0_vm_fault_interrupt_state()
608 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_hpd_irq_state()639 st = (state == AMDGPU_IRQ_STATE_ENABLE); in dm_irq_state()