Searched refs:ADDR_MASK (Results 1 – 9 of 9) sorted by relevance
66 #define RCR(addr) (RCRCODE | (addr & ADDR_MASK)) /* Read Control Register */67 #define WCR(addr) (WCRCODE | (addr & ADDR_MASK)) /* Write Control Register */70 #define BFS(addr) (BFSCODE | (addr & ADDR_MASK)) /* Bit Field Set */71 #define BFC(addr) (BFCCODE | (addr & ADDR_MASK)) /* Bit Field Clear */89 #define ADDR_MASK 0x1F macro
69 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_read()120 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_update()
19 #define ADDR_MASK 0x1F macro
156 tx_buf[0] = op | (addr & ADDR_MASK); in spi_read_op()175 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK); in spi_write_op()
34 base = rom_vector[EXT_IRQ0] & ADDR_MASK; in get_vector_address()39 (rom_vector[vec_no] & ADDR_MASK)) in get_vector_address()
27 #define ADDR_MASK (0xffffff) macro
45 #define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */ macro50 ((unsigned int)(JAL | (((addr) >> 2) & ADDR_MASK)))
333 adrmask = ioread32(&hw->reg->ADDR_MASK); in pch_gbe_mac_mar_set()334 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK); in pch_gbe_mac_mar_set()336 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); in pch_gbe_mac_mar_set()341 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK); in pch_gbe_mac_mar_set()343 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); in pch_gbe_mac_mar_set()395 iowrite32(0xFFFE, &hw->reg->ADDR_MASK); in pch_gbe_mac_init_rx_addrs()397 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); in pch_gbe_mac_init_rx_addrs()459 wu_evt, ioread32(&hw->reg->ADDR_MASK)); in pch_gbe_mac_set_wol_event()463 addr_mask = ioread32(&hw->reg->ADDR_MASK); in pch_gbe_mac_set_wol_event()2132 adrmask = ioread32(&hw->reg->ADDR_MASK); in pch_gbe_set_multi()[all …]
62 u32 ADDR_MASK; member
