Searched refs:A7 (Results 1 – 25 of 68) sorted by relevance
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| /Linux-v5.4/arch/c6x/lib/ |
| D | csum_64plus.S | 45 LDW .D1T1 *A4++,A7
47 MV .S2X A7,B7
48 || EXTU .S1 A7,0,16,A16
66 LDNW .D1T1 *A4++,A7
70 MV .S2X A7,B7
71 || EXTU .S1 A7,0,16,A16
72 || MPYU .M1 A7,A2,A8
84 ZERO .L1 A7
89 LDBU .D1T1 *A4++,A7
92 SHL .S1 A7,8,A0
[all …]
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| D | strasgi.S | 19 ldw .d2t1 *B4++, A7
43 || mv .s2x A7, B5
46 [B0] ldw .d2t1 *B4++, A7
70 [B0] stw .d1t1 A7, *A4++
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| D | memcpy_64plus.S | 20 [A1] LDB .D2T1 *B4++,A7
28 [A1] STB .D1T1 A7,*A3++
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| D | remu.S | 13 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
36 mv .l1x B1, A7
68 extu .s1 A4, A7, A4
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| D | divi.S | 13 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
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| D | remi.S | 13 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
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| /Linux-v5.4/Documentation/arm/ |
| D | sunxi.rst | 47 * Single ARM Cortex-A7 based SoCs
54 * Dual ARM Cortex-A7 based SoCs
71 * Quad ARM Cortex-A7 based SoCs
123 * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
130 * Octa ARM Cortex-A7 based SoCs
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| /Linux-v5.4/arch/arm/include/debug/ |
| D | exynos.S | 27 teq \tmp, #0x100 @@ A15 + A7 but boot to A7
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| /Linux-v5.4/arch/arm/boot/dts/ |
| D | vexpress-v2p-ca15_a7.dts | 275 /* A7 PLL 0 reference clock */
284 /* A7 PLL 1 reference clock */
349 /* A7 CPU core voltage */
352 regulator-name = "A7 Vcore";
356 label = "A7 Vcore";
367 /* Total current for the three A7 cores */
370 label = "A7 Icore";
388 /* Total power for the three A7 cores */
391 label = "A7 Pcore";
402 /* Total energy for the three A7 cores */
[all …]
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| D | exynos5422-cpus.dtsi | 8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
16 * from the LITTLE: Cortex-A7.
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| D | exynos5422-odroidxu3.dts | 44 /* A7 cluster: VDD_KFC */
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| D | exynos5420-cpus.dtsi | 17 * from the LITTLE: Cortex-A7.
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| /Linux-v5.4/arch/arm/mach-prima2/ |
| D | Kconfig | 28 bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform"
35 Support for CSR SiRFSoC ARM Cortex A7 Platform
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| /Linux-v5.4/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx7ulp-pinctrl.txt | 3 i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
7 This binding doc is only for the IOMUXC1 support in A7 Domain and it only
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| /Linux-v5.4/Documentation/devicetree/bindings/clock/ |
| D | imx7ulp-clock.txt | 8 and A7 domain. Except for a few clock sources shared between two
14 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
16 Note: this binding doc is only for A7 clock domain.
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| D | brcm,bcm53573-ilp.txt | 8 on Broadcom BCM53573 devices using Cortex-A7 CPU.
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| /Linux-v5.4/Documentation/admin-guide/device-mapper/ |
| D | dm-raid.rst | 129 A4 A4 A5 A6 A6 A7 A7 A8 A8
145 A3 A4 A4 A5 A6 A5 A6 A7 A8
146 A5 A6 A7 A8 A9 A9 A10 A11 A12
149 A4 A3 A6 A4 A5 A6 A5 A8 A7
150 A6 A5 A9 A7 A8 A10 A9 A12 A11
162 A3 A4 A4 A5 A6 A5 A6 A7 A8
163 A4 A3 A6 A4 A5 A6 A5 A8 A7
164 A5 A6 A7 A8 A9 A9 A10 A11 A12
165 A6 A5 A9 A7 A8 A10 A9 A12 A11
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| /Linux-v5.4/arch/arm/mach-exynos/ |
| D | Kconfig | 57 Samsung EXYNOS3 (Cortex-A7) SoC based systems
74 Samsung EXYNOS5 (Cortex-A15/A7) SoC based systems
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| /Linux-v5.4/Documentation/arm/stm32/ |
| D | stm32mp157-overview.rst | 11 - Dual core Cortex-A7 application core
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| /Linux-v5.4/tools/perf/arch/riscv/util/ |
| D | unwind-libdw.c | 38 dwarf_regs[17] = REG(A7); in libdw__arch_set_initial_registers()
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| /Linux-v5.4/Documentation/devicetree/bindings/timer/ |
| D | nxp,sysctr-timer.txt | 4 a shared time base to Cortex A15, A7, A53, A73, etc. it is intended for use in
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| /Linux-v5.4/arch/arc/plat-eznps/ |
| D | entry.S | 14 .cpu A7
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| /Linux-v5.4/arch/mips/boot/dts/pic32/ |
| D | pic32mzda_sk.dts | 102 pins = "A6", "D4", "G13", "G12", "G14", "A7", "A0";
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| /Linux-v5.4/arch/arm/mach-vexpress/ |
| D | Kconfig | 34 - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
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| /Linux-v5.4/Documentation/ABI/testing/ |
| D | sysfs-driver-genwqe | 16 Description: Type of the card e.g. 'GenWQE5-A7'.
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